Automatic extraction technique of CD‐SEM evaluation points to measure semiconductor overlay error

Abstract

AbstractIn semiconductor device manufacturing process, it is necessary to measure overlay error between integrated layers. As semiconductor process design rules continue to shrink, small overlay error comes to lead to the fatal fault of the device electrical property. As a result, the needs for the dense overlay measurement in the chip with the use of circuit pattern increase. We propose an automatic extraction technique of the evaluation points (EPs) that are suitable for the overlay measurement by scanning electron microscopy using design data of the device pattern layout. The proposed algorithm extracts all measureable patterns by evaluation of the positional relationship between a segment pair on the upper and lower layers by plural selection indices. Simulation was performed to estimate the overlay error distribution within the shot area using the EPs automatically extracted by the proposed method. The standard deviations of estimation errors in the x‐ and y‐directions were 0.06 nm and 0.10 nm (3ó), respectively. It was confirmed that distortion in the exposure apparatus can be estimated automatically and highly accurately.