Study of critical dimension and overlay measurement methodology using SEM image analysis for process control

Abstract

As the design rule of semiconductor devices shrinks to below 100nm dimensions, the degree of pattern alignment from different process levels has become a crucial factor affecting both process control and induced defect on unit process. Isolated and dense patterns were formed at process layers from front-end through to back-end on wafers using sub 100nm device process utilizing ArF lithography under various lithography conditions. As pattern size is reduced, overlay discrepancies become larger. The OL (overlay) error is very important because the pattern misalignment induces critical defects for the device. For many years, overlay metrology for process control has been measured by 4-corner box-in-box methods in chip. OL errors and CD (Critical Dimension) values have been measured on different tool. CD values have been measured on SEMs (Scanning Electron Microscope) and OL errors have been measured on optical tools. The accuracy of OL error metrology is limited by the resolution of tool, which is on the order of 1μm. In this paper we calculated the degree of overlay errors (current level to prior level errors) through a process patterns images obtained from a CD-SEM.