Simultaneous critical dimension and overlay measurements on a SEM through target design for inline manufacturing lithography control

Abstract

This paper introduces the capability of measuring overlay (OL) errors (current level to prior level errors and neighboring field errors) and critical dimension (CD) errors simultaneously on a Critical Dimension Scanning Electron Microscope (CD SEM). In the past OL errors and CD errors have been measured on different tools sets. CD errors have always been measured on SEMs and OL errors have always been measured on optical tools. In both cases, measurements were obtained on separate target designs. The key to this paper is in the design of the targets. We combine, in one target design, the ability to extract OL and CD errors simultaneously. Current OL targets designs are limited by the resolution of that type of tool which is on the order of 1um, this means that current OL target designs are created at ground rules larger than this (typically 2-3um in size) and at ground rules much larger than the circuit design. A target design that allows the OL and CD to be measured at the ground rules of the circuit would be a much more desirable measurement and takes advantage of the SEM's strengths which include resolution. Additionally, a target design that allows current level to prior level OL, neighboring field OL and CD errors to be measured simultaneously would be extremely desirable. The key is designing the targets for cases where prior level information can be seen on the SEM, this can be performed on many levels throughout chip construction, probably more than half of all levels. This methodology will significantly reduce the time it takes to build parts, improve technical performance and save tool cost.