Oversampling Ratio Research Articles

A Reconfigurable 12-to-18-Bit Dynamic Zoom ADC With Pole-Optimized Technique

This paper presents a resolution-reconfigurable discrete-time dynamic zoom analog-to-digital converter (ADC) with a 20-kHz bandwidth. It employs a coarse 6-bit successive approximation register (SAR) ADC that dynamically updates the references for the post-stage single-bit second-order delta-sigma modulator to obtain a higher resolution with lower power. The sampling rate of the proposed ADC can be configured to be 1.6, 3.2, 6.4 and 10-MS/s such that four resolution modes, including 12, 14, 16 and 18-bit, can be provided accordingly. Note that pole locations of the noise transfer function (NTF) vary with different OSR’s, and noise-shaping effect, together with the power efficiency, can be degraded. To solve this issue, the pole-optimization technique is proposed in this paper. In this way can the pole locations be reconfigured according to the specific OSR. Additionally, the bandwidths of the operational amplifiers are also modulated in different oversampling ratio (OSR) scenarios to further improve the energy efficiency. Fabricated in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> m CMOS process, the prototype occupies 1.01 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> . On condition of an OSR of 250, the proposed ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) of 102.8 dB, while dissipating 1.3 mW.

Effective Variational-Autoencoder-Based Generative Models for Highly Imbalanced Fault Detection Data in Semiconductor Manufacturing

In current semiconductor manufacturing, limited raw trace data pertaining to defective wafers make fault detection (FD) assignments extremely difficult due to the data imbalance in wafer classification. To mitigate, this paper proposes using a variational autoencoder (VAE) as a data augmentation strategy for resolving data imbalance of temporal raw trace data. A VAE with few defective samples is first trained. By means of extracting the latent variables that characterize the distribution of the defective samples, we make use of the statistical randomness of the latent variables to generate synthesized defective samples via the decoder scheme in the trained VAE. Two data representations and VAE modeling strategies, concatenation of multiple and individual raw trace data as the input of the VAE during the training stage, are investigated. A real-data plasma enhanced chemical vapor deposition (PECVD) process having only few defective samples is used to illustrate the performance enhancement to wafer classification arising from the proposed data augmentation framework. Based on the computational comparisons between noted classification models, the proposed generative VAE model via the individual strategy enables the adaptive boosting (AdaBoost) classifier to achieve perfect performances in every metrics if the 80% and 100% over-sampling ratios are adopted.

9.9 µW, 140 dB DR, and 93.27 dB SNDR, Double Sampling ΔΣ Modulator Using High Swing Inverter-Based Amplifier for Digital Hearing Aids

In this paper, an ultra-low-power second-order, single-bit discrete-time (DT) double sampling ΔΣ modulator was proposed for hearing aid applications. In portable biomedical devices that are permanently used such as hearing aids, short battery lifetime and power dissipation are considerable issues. In a typical delta–sigma modulator, the most power-consuming parts are the operational transconductance amplifiers (OTAs), and their elimination without loss of efficiency is now challenging. This proposed modulator includes an ultra-low-power self-biased inverter-based amplifier with swing enhancement instead of power-hungry OTAs. Low voltage amplifier design reduces output swing voltage, affecting delta–sigma modulator efficiency and decreasing the signal-to-noise and distortion ratio (SNDR) and dynamic range (DR) values. In this article, the proposed amplifier’s source and tail transistors were biased in the sub-threshold region, increasing the output swing voltage significantly and leading to desired properties for a hearing aid modulator. The proposed amplifier peak-to-peak swing voltage was approximately 1.01 V at a 1 V power supply. In addition, the proposed modulator design used a standard 180 nm CMOS technology, which obtained 140 dB DR and 93.27 dB SNDR for a 10 kHz signal bandwidth with an oversampling ratio (OSR) of 128. Finally, the modulator’s effective chip area was 0.02 mm2 and consumed only about 9.9 µW, while the figure of merit (FOMW) and FOMs achieved 1.31 fJ/step and 183.31, respectively.

A Σ-Δ Modulator Based on an Inverter-based Integrator with Dynamic Current Switch

This paper presents a low-power high-resolution 3rd-order 1-bit Σ-Δ modulator based on an inverter-based integrator with a dynamic current switch. To reduce the power consumption of the modulator circuit, a dynamic current switch branch is added to form a low-power inverter-based integrator. A 3rd-order 1-bit Σ-Δ modulator is designed in a TSMC 65 nm CMOS technology to verify the effectiveness of the proposed integrator circuit. The prototype Σ-Δ modulator achieves 102.4 dB SNDR, 16.71 Bit ENOB in a 2 KHz signal BW at an Over Sampling Ratio (OSR) of 160, while consuming only 29.5-μW. And the FOMSNDR is 180.7 dB.

A Single-Loop Third-Order 10-MHz BW Source-Follower-Integrator Based Discrete-Time Delta-Sigma ADC

This brief presents a single-loop third-order discrete-time delta-sigma ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ {\Delta } {\Sigma }$ </tex-math></inline-formula> ) analog-to-digital converter (ADC). The proposed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ {\Delta } {\Sigma }$ </tex-math></inline-formula> ADC employs source-follower (SF)-based open-loop switched-capacitor (SC) integrators to achieve high-speed operation with efficient power consumption. A modified feed-forward topology is proposed to improve the linearity of the modulator using the SF-based integrators. An interpolating 4-bit flash quantizer with an embedded data weighted averaging (DWA) function is employed to address the nonlinearity of the feedback digital-to-analog converter (DAC) for high speed operation. The prototype ADC implemented in a 65nm CMOS technology achieves 75.4-dB dynamic range (DR) and 73.3-dB peak signal-to-noise-and-distortion ratio (SNDR) over 10-MHz bandwidth with an oversampling ratio (OSR) of 16. The power consumption of the modulator is 13.3-mW from a 1.1-V supply, resulting in the Walden and Schreier figure-of-merits (FoMW and FoMS) of 174-fJ/conversion-step and 164-dB, respectively.

Design and Implementation of a Second Order Continuous-Time ΣΔ Modulator for ECG Signal Acquisition

The recent developments in biosignal acquisition devices for continuous supervision of cardiovascular signs of high-risk patients require a high-precision and low-power Analog Front End (AFE) circuit. The proposed design adopts Continuous-Time (CT) Sigma-Delta Modulator (ΣΔM) architecture to achieve high resolution and SIgnal-to-Noise And Distortion ratio (SINAD) requirements. The proposed modulator is a second-order CT-ΣΔM with Cascade of Integrators Feed-Forward (CIFF) architecture that consists of a CT loop filter, a single-bit quantizer, and a Digital-to-Analog Converter (DAC). The use of single-bit quantization in the design reduces circuit complexity and power consumption. To use the designed ΣΔM for measuring ECG signals, a bandwidth (Bw) of 150 Hz is considered with a sampling frequency (fs) of 153.6kHz to achieve an oversampling ratio of 512. The design is simulated in a standard Cadence Virtuoso EDA tool at 180nm CMOS technology, operating at 1.8V supply voltage at the block level. The simulation results for the designed modulator show that SINAD is 104.5dB, the Effective Number Of Bits (ENOB) is 17.06bits, with power consumption of 24µW, and achieves Schreier’s Figure-Of-Merit (FOM) equal to 172.45dB.

A 2.5-MHz BW, 75-dB SNDR Noise-Shaping SAR ADC With a 1st-Order Hybrid EF-CIFF Structure Assisted by Unity-Gain Buffer

This article presents a 1st-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a hybrid error-feedback (EF) and cascaded-integrator-feed-forward (CIFF) structure assisted by a unity-gain buffer (UGB). Without using a multi-input comparator which is widely adopted in conventional 1st-order passive NS structures, the proposed hybrid EF-CIFF structure realizes a more ideal 1st-order noise transfer function (NTF) with a reasonable capacitance ratio, so as to obtain better NS effect. Fabricated in a 28-nm CMOS technology, the prototype NS-SAR ADC consumes 150 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> under a 0.9-V supply voltage when operating at 40-MS/s sampling rate. A 75-dB signal-to-noise-and-distortion ratio (SNDR) is measured for a 2.47-MHz sinusoid input under an oversampling ratio (OSR) of 8. It achieves a peak Schreier figure-of-merit (FoM) of 177.2 dB and the core circuit occupies 0.012-mm2 area.

A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs

Continuous-time pipelined (CTP) ADCs have shown the potential to alleviate the challenges of discrete-time (DT) pipelined converters with Multi-GHz bandwidth, but have so far required an oversampling ratio (OSR) of at least 4. After elucidating the factors that limit CTP bandwidth, this paper presents a design methodology for near-Nyquist CTP ADCs. The delay circuit is optimized to match the ADC/DAC path in both its broadband magnitude response and phase. The residue filter response is optimized to prevent image signals from overloading the subsequent stage. We show that practical circuits can realize these optimized responses and extend the bandwidth of the CTP architecture to OSRs of 1.5-2.0, essentially equivalent to the OSR of DT converters when allowing for practical anti-aliasing. The direct path (i.e. delay) and the residue-amplifying filter circuits required for 3 GHz bandwidth are incorporated into a complete 4-bit 10 GS/s CTP ADC stage in a 28nm CMOS prototype. Simulation and measurement results confirm that CTP ADCs can operate at a near-Nyquist sampling rate with an OSR of 1.7.

Blind Symbol-Rate Estimation for Short and Bursty Communications

The design of a blind receiver for unsynchronized bursty communications is a challenging task, especially when the data burst duration is very short and the over-sampling ratio (OSR) at the receiver is a non-integer value. In this article, the problem of blind symbol-rate estimation for bursty communications is studied. A cyclostationary method with bias removal (CS-BR) is proposed to improve the accuracy of the “OSR peak” detection in cyclostationary method when the length of signal burst is very short. Factors which affect the accuracy of the proposed blind symbol-rate estimation are thoroughly analyzed. Both field measurement data simulations and Monte Carlo simulations show that by using our proposed CS-BR method, the accuracy of blind symbol-rate estimation can be significantly improved, and the root-mean-square-error of the estimated OSR can be reduced to as small as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$10^{-4}$</tex-math></inline-formula> even if each short data burst consists of only tens of symbols.

A Low-Resolution Direct Digital Synthesis Transmitter Architecture Using Dithering for Multiband 5G NR Mobile Applications

This letter presents a low-resolution multiband transmitter architecture using direct digital synthesis (DDS) with dithering. Modern modulated signals constructed by a low-resolution digital-to-analog converter (DAC) suffer from quantization errors and distortions. The proposed technique reduces the quantization problems with the use of a proper oversampling ratio (OSR) and the dithering technique. This technique has lower cost and lower complexity compared to conventional transmitters while maintaining linearity performance. A 50-MHz 5G NR 256-quadratic-amplitude modulation (QAM) signal is used for concept validation at bands n1, n40, and n50. The proposed work achieved the adjacent channel leakage ratio (ACLR) and error vector magnitude (EVM) requirements of under −30 dBc and 3.5%, respectively. A single 3-bit 10-GS/s radio frequency (RF) DAC is used where the performance is similar to a conventional transmitter using a pair of 5-bit baseband in-phase and quadrature (IQ) DACs.

A 4th-Order Continuous-Time Delta-Sigma Modulator With Hybrid Noise-Coupling

A hybrid noise-coupling (HNC) technique is proposed to mitigate the issues with a digital noise-coupling (DNC) structure. In the proposed technique, the unwanted quantization noise that is generated from the noise-coupling analog-to-digital converter (ADC) is injected into the input of the quantizer with one-clock cycle delay, thus increasing the order of noise-shaping of this error. Behavioral simulation shows that the HNC is highly robust against gain variation. The proposed fourth-order continuous-time (CT) delta-sigma modulator (DSM) with HNC scheme was designed in a 28-nm CMOS technology with a core size of 0.3mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . With an oversampling ratio (OSR) of 32, the proposed design achieves a signal-to-noise-distortion ratio (SNDR) of 97.20-dB at a signal bandwidth of 15.625-kHz, which has a 7-dB improvement in comparison to DNC only without introducing significant hardware complexity.

Delta-Sigma Modulator-Embedded Digital Predistortion for 5G Transmitter Linearization

This article presents two novel digital predistortion (DPD) based architectures that jointly mitigate the inphase/quadrature (IQ) modulator impairments and the power amplifier (PA) nonlinear distortion in wireless transmitters. The proposed architectures are multibit cartesian and complex delta-sigma modulator-based joint DPDs, called CDSM-JDPD and CXDSM-JDPD, respectively, which enable using low-cost digital-to-analog converters (DACs) while offering versatile linearization capabilities to combat the coexisting distortions of the PA and the IQ modulator. The proposed approach alleviates the need for reverse modeling and implementation of extra hardware to separately deal with frequency-dependent IQ impairments. Moreover, the CXDSM-JDPD enhances the linearization performance and relaxes the high oversampling ratio (OSR) requirement by quantizing the signal more efficiently. Furthermore, the presented concepts inherently support the use of low-resolution DACs, which offers a tremendous advantage in designing and implementing low-cost and energy-efficient radio transmitters. Extensive set of hardware-in-the-loop RF verification measurements with a commercial PA are provided, including two timely 5G New Radio (NR) scenarios at NR bands n3 and n78, while covering channel bandwidths up to 100 MHz and varying the OSR and the DAC bit resolution. The obtained results demonstrate the excellent linearization capabilities of the proposed solutions and their superiority compared to other DSM-based DPD approaches.

Quantization for Spectral Super-Resolution

We show that the method of distributed noise-shaping beta-quantization offers superior performance for the problem of spectral super-resolution with quantization whenever there is redundancy in the number of measurements. More precisely, we define the over-sampling ratio \(\lambda \) as the largest integer such that \(\lfloor M/\lambda \rfloor - 1\ge 4/\Delta \), where M denotes the number of Fourier measurements and \(\Delta \) is the minimum separation distance associated with the atomic measure to be resolved. We prove that for any number \(K\ge 2\) of quantization levels available for the real and imaginary parts of the measurements, our quantization method combined with either TV-min/BLASSO or ESPRIT guarantees reconstruction accuracy of order \(O(M^{1/4}\lambda ^{5/4} K^{- \lambda /2})\) and \(O(M^{3/2} \lambda ^{1/2} K^{- \lambda })\), respectively, where the implicit constants are independent of M, K and \(\lambda \). In contrast, naive rounding or memoryless scalar quantization for the same alphabet offers a guarantee of order \(O(M^{-1}K^{-1})\) only, regardless of the reconstruction algorithm.

Design and Implementation of Decimation Filter for 13-bit Sigma-Delta ADC Based on FPGA

A 13 bit Sigma-Delta ADC for a signal band of 40K Hz is designed in MATLAB Simulink and then implemented using Xilinx system generator tool. The first order Sigma-Delta modulator is designed to work at a signal band of 40 KHz at an oversampling ratio (OSR) of 256 with a sampling frequency of 20.48 MHz. The proposed decimation filter design is consists of a second order Cascaded Integrator Comb filter (CIC) followed by two finite impulse response (FIR) filters. This architecture reduces the need for multiplication which is need very large area. This architecture implements a decimation ratio of 256 and allows a maximum resolution of 13 bits in the output of the filter. The decimation filter was designed and tested in Xilinx system generator tool which reduces the design cycle by directly generating efficient VHDL code. The results obtained show that the overall Sigma-Delta ADC is able to achieve an ENOB (Effective Number Of Bit) of 13.71 bits and SNR of 84.3 dB.

A 625kHz-BW, 79.3dB-SNDR Second-Order Noise-Shaping SAR ADC Using High-Efficiency Error-Feedback Structure

This brief presents a compact and energy efficient noise-shaping successive-approximation-register (NS-SAR) analog-to-digital converter (ADC) based on the error-feedback (EF) structure. Different from most prior works adopting the cascaded integrator feed-forward (CIFF) structure, the proposed architecture employs unity-gain buffer and delay elements operated in a ping-pong manner to perform EF function. Since to the lossless residue extraction and summation, it exhibits high efficiency in realizing the strong noise-shaping (NS) effect. Fabricated in a 65-nm 1P9M CMOS technology, the prototype NS-SAR ADC consumes <inline-formula> <tex-math notation="LaTeX">$113.02~\mu \text{W}$ </tex-math></inline-formula> when operating at a 1.2-V supply voltage and at a sampling rate of 20 MS/s. It achieves a peak Schreier FoM of 176.73 dB with a signal to noise and distortion-ratio (SNDR) of 79.3 dB at an oversampling ratio (OSR) of 16.

A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC With Gain and Offset Calibrations

This article presents a second-order successive approximation register (SAR)-assisted noise-shaping (NS) pipeline analog-to-digital converter (ADC) with optimized noise transfer function (NTF) zeros, background inter-stage gain, and offset calibrations. The NS, realized with an error-feedback (EF) structure, takes place in the second stage of the pipeline. A single amplifier, utilized for residue handover, realizes the EF and the optimized zeros. Copies of the EF capacitors allow their rotation role for residue saving, feedback, and sampling operations, thus omitting the extra phase for the EF operation. While further incorporating a coarse SAR ADC and partial interleaving techniques, the prototype can run at high speed with low power and strong in- band noise suppression. A split-over-time architecture with level-shift-based gain calibration is introduced to ensure the robustness of the ADC, whose hardware also facilitates the offset calibration. Besides, the split second-stage ADCs also share a single comparator, thus enabling a mismatch error insensitive split-ADC architecture with a fast convergence speed of 4000 cycles. Fabricated in 28 nm CMOS, the ADC prototype runs at a 260 MHz sampling rate and retains 20 MHz bandwidth (BW) with a signal-to-noise-and-distortion ratio (SNDR) of 79.1 dB under a small over-sampling ratio (OSR) of 6.5. It consumes 3.1 mW power at a 1 V supply and yields a Schreier figure-of-merit (FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</sub> ) of 177.2 dB.

A 1.01 NEF Low-Noise Amplifier Using Complementary Parametric Amplification

This paper presents a discrete-time low-noise amplifier for miniaturized sensor nodes. Such amplifier achieves a noise efficiency factor of 1.01 and a power efficiency factor of 1.63, improving the noise efficiency of an analog front-end. The proposed preamplifier employs discrete-time parametric amplification by modulating the capacitance of a MOS varactor. The sampling noise is minimized by adopting a high oversampling ratio of the input voltage, leading to an input-referred noise of 520 nV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> in a 1 kHz bandwidth. Also, the power consumption is reduced by using a 34-phase stepwise charging technique. The multiphase soft-charging technique is implemented using multiple time-interleaved cells and allows to significantly reduce the current consumption without introducing any significant penalty in terms of additional noise or area occupation. A two-stage parametric amplifier is introduced to provide higher gain, and suppress the noise contribution of the following amplifier chain. The proposed two-stage complementary preamplifier is followed by a third continuous-time stage, that employs a current-reuse inverter-based architecture. The contribution to the total noise efficiency factor of such amplifier is attenuated by the gain of the previous two-stage parametric preamplifier. As a result, the third stage provides gain programmability, while degrading the NEF of the entire chain by less than 10%.

Linear Bayesian Approaches for Low-Oversampled Stepwise Staggered SAR Data

Staggered synthetic aperture radar (SAR) is an innovative concept to obtain an ultrawide continuous swath with fine azimuth resolution using multiple elevation beams and pulse repetition interval (PRI) variation. Conventionally, the interpolation of the nonuniform data with gaps (due to the interruption during transmission, i.e., blockage) requires a high oversampling ratio to avoid image quality degradation, which leads to increased range ambiguities and high downlink data rates. In recent years, there has been a growing interest in improving the image quality for low-oversampled staggered mode. This study suggests a new concept, stepwise staggered SAR, which employs stepwise staggered PRIs to facilitate the use of novel linear Bayesian approaches to achieve high-quality recovery of blockage in low-oversampled data. The so-called step in “stepwise” refers to a period that contains multiple constant PRIs in a PRI staggering cycle, ensuring part of the data uniformly sampled to reduce the error propagation during resampling. In addition to the no-consecutive gap condition, the stepwise PRI staggering strategy meets the requirement of no more than one gap at any location within the slant range of interest in each PRI staggering cycle, which makes it possible to easily extract prior information from the consecutive known samples on both sides of each blockage sample to realize the proposed linear Bayesian approaches. Because the prior information adapts to characteristics of backscatter, the linear Bayesian estimation has an excellent performance in blockage recovery, which has been validated by simulations with different scenarios.

A 13.8-ENOB Fully Dynamic Third-Order Noise-Shaping SAR ADC in a Single-Amplifier EF-CIFF Structure With Hardware-Reusing kT/C Noise Cancellation

To design noise-shaping successive approximation register (NS-SAR) analog-to-digital converters (ADCs) with high resolution and good power efficiency, two key bottlenecks need to be addressed. One is to realize a high-order loop filter with low circuit overhead, and the other is to mitigate the thermal noise. This article presents an NS-SAR ADC that synergistically addresses both challenges. To achieve high-order efficiency, it proposes an innovative error feedback-cascaded integrator feedforward (EF-CIFF) structure that realizes third-order noise shaping using only a single amplifier. It combines the merits of both structures, showing improved robustness, and is free of dc offset concern. On reducing the kT/C noise, this work features a sampling kT/C noise cancellation (SNC) technique that reuses the native hardware of the EF-CIFF structure. An open-loop self-quenching floating-inverter dynamic amplifier (FIDA) is used to support all amplification with low noise and power. Prototyped in 65-nm CMOS, this work achieves 84.8-dB signal-to-noise-distortion ratio (SNDR) with 625-kHz bandwidth (BW) (OSR = 8) and 119 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> , leading to 182-dB Schreier Figure of Merit (FoM). It uses only 0.8-pF input capacitance, which is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5\times $ </tex-math></inline-formula> smaller than prior NS-SAR ADCs with similar oversampling ratio (OSR) and SNDR.

A Pipelined Noise-Shaping SAR ADC Using Ring Amplifier

In this study, a pipelined noise-shaping successive-approximation register analog-to-digital converter (PLNS-SAR ADC) structure was proposed to achieve high resolution and to be free from comparator design requirements. The inter-stage amplifier and integrator of the PLNS-SAR ADC were implemented through a ring amplifier with high gain and speed. The ring amplifier was designed to improve power efficiency and be tolerant to process–voltage–temperature (PVT) variation, and uses a single loop common-mode feedback (CMFB) circuit. By processing residual signals with a single ring amplifier, power efficiency can be maximized, and a low-power system with 30% lower power consumption than that of a conventional PLNS-SAR ADC is implemented. With a high-gain ring amplifier, noise leakage is greatly suppressed, and a structure can be implemented that is tolerant of mismatches between the analog loop and digital correction filters. The measured signal to noise distortion ratio (SNDR) is 70 dB for a 5.15 MHz bandwidth (BW) at a 72 MS/s sampling rate (Fs) with an oversampling ratio (OSR) of 7, and the power consumption is 2.4 mW. The FoMS,SNDR (= SNDR + 10log10BW/Power) is 163.5 dB. The proposed structure in this study can achieve high resolution and wide BW with good power efficiency, without a filter calibration process, through the use of a ring amplifier in the PLNS-SAR ADC.