Gate Output Research Articles

Categorical representation of objects in the central nucleus of the monkey amygdala

The primate amygdala consists of several subnuclei. Neurons in this brain area have been known to respond to stimuli belonging to specific categories of objects, such as faces, animals, and artifacts. However, little is known about the functional differences among the nuclei of the primate amygdala. To clarify functional differences among these subnuclei in object categorization, we compared the responsiveness of neuronal populations among the lateral, basal and central nuclei of the monkey amygdala. The activity of 203 neurons was recorded while video clips of 13 stimuli belonging to three categories (monkey, human, and artifact) were presented. Of these neurons, 37, 39 and 37 neurons in the lateral, basal and central nuclei, respectively, responded to at least one of the stimuli. We applied a cluster analysis to the neuronal population responses from these nuclei, and also calculated information about the three categories and monkey identity from each neuronal population. We found that the three categories and monkey identity could be more properly classified by neuronal responsiveness in the central nucleus, which is an output gate of the amygdala, than by that in the lateral and basal nuclei. These results suggest that the information about objects suitable for the generation of appropriate emotional response is built up within the primate amygdala via an intra-amygdala network from the lateral nucleus to the central nucleus.

Enzyme-Based Logic Analysis of Biomarkers at Physiological Concentrations: AND Gate with Double-Sigmoid “Filter” Response

We report the first realization of a biomolecular AND gate function with double-sigmoid response (sigmoid in both inputs). Two enzyme biomarker inputs activate the gate output signal, which can then be used as indicating liver injury, but only when both of these inputs have elevated pathophysiological concentrations, effectively corresponding to logic-1 of the binary gate functioning. At lower, normal physiological concentrations, defined as logic-0 inputs, the liver-injury output levels are not obtained. High-quality gate functioning in handling of various sources of noise, on time scales of relevance to potential applications, is enabled by utilizing "filtering" effected by a simple added biocatalytic process. The resulting gate response is sigmoid in both inputs when proper system parameters are chosen, and the gate properties are theoretically analyzed within a model devised to evaluate its noise-handling properties.

A method for synthesis of easily-testable circuits in some basis admitting single fault detection tests of constant length

A method of synthesis of irredundant circuits of functional elements in the basis {x&y, x⊕y, 1, \(\bar x\)(y ∨ z) ∨ x(y ∼ z)} realizing arbitrary Boolean functions and admitting unit verification tests of the length not exceeding 4 is proposed in the paper for inverse or constant (stuck-at) faults at outputs of gates.

An Integrated Amorphous Silicon Gate Driver Circuit Using Voltage-Controlled Capacitance Modeling for High Definition Television

We have developed the integrated amorphous silicon gate driver circuit using the model extraction technique of the inverted staggered and nonsymmetric amorphous silicon (a-Si) thin film transistor. The relation between capacitance characteristics of hydrogenated a-Si (a-Si:H) integrated transistors and the output signal of the gate driver circuit is analyzed using UTMOST IV ver. 1.6.4.R and SMARTSPICE ver. 3.19.15.C. The accuracy of the simulated gate output signal using voltage-controlled capacitance modeling is verified with measured data. The a-Si gate driver circuit using the proposed (TFT) model increased the accuracy of rising (95.3%) and falling (92%) time, compared to the conventional model. The suggested model extraction technique can be used for bottom gate and asymmetric TFT structures.

An Integrated Amorphous Silicon Gate Driver Circuit Using Voltage-Controlled Capacitance Modeling for High Definition Television

We have developed the integrated amorphous silicon gate driver circuit using the model extraction technique of the inverted staggered and nonsymmetric amorphous silicon (a-Si) thin film transistor. The relation between capacitance characteristics of hydrogenated a-Si (a-Si:H) integrated transistors and the output signal of the gate driver circuit is analyzed using UTMOST IV ver. 1.6.4.R and SMARTSPICE ver. 3.19.15.C. The accuracy of the simulated gate output signal using voltage-controlled capacitance modeling is verified with measured data. The a-Si gate driver circuit using the proposed (TFT) model increased the accuracy of rising (95.3%) and falling (92%) time, compared to the conventional model. The suggested model extraction technique can be used for bottom gate and asymmetric TFT structures.

Effects of dry oxidation of heavily doped p-type Si on output and transfer characteristics in organic thin film transistors

► A SiO 2 layer was grown on the heavily doped p-type Si using a dry oxidation process. ► The effect of an O 2 gas flow on the quality of thermally growing SiO 2 was examined. ► A low O 2 gas flow led to the formation of the intermediate oxygen deficient oxide. ► The significant gate leakage is the major source of the drain offset. This paper presents an analysis of the effect of the SiO 2 /Si interfacial property on output (transfer) characteristics of organic thin film transistors (OTFTs). A SiO 2 layer was grown on the heavily doped p-type Si wafer using a dry oxidation process as a gate oxide layer. The electrical conduction investigations suggest that the leakage behavior is governed by the poor insulation of the oxygen deficient oxide between SiO 2 and Si. From the observed result, the relationship between gate leakage and output (transfer) characteristics of OTFTs was discussed.

Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability

With lower supply voltages, increased integration densities and higher operating frequencies, power grid verification has become a crucial step in the very large-scale integration design cycle. The accurate estimation of maximum instantaneous power dissipation aims at finding the worst-case scenario where excessive simultaneous switching could impose extreme current demands on the power grid. This problem is highly input-pattern dependent and is proven to be NP-hard. In this paper, we capitalize on the compelling advancements in satisfiability (SAT) solvers to propose a pseudo-Boolean SAT-based framework that reports the input patterns maximizing circuit activity, and consequently peak dynamic power, in combinational and sequential circuits. The proposed framework is enhanced to handle unit gate delays and output glitches. In order to disallow unrealistic input transitions, we show how to integrate input constraints in the formulation. Finally, a number of optimization techniques, such as the use of gate switching equivalence classes, are described to improve the scalability of the proposed method. An extensive suite of experiments on ISCAS85 and ISCAS89 circuits confirms the robustness of the approach compared to simulation-based techniques and encourages further research for low-power solutions using Boolean SAT.

Repairable Fault Tree Analysis Using Renewal Intensities

Fault tree (FT) is one of powerful tools for reliability analysis. The conventional FT usually considers only failure occurrence as an input event. However, considering repair in FT improves the analysis capability of FT. This FT is referred to as a repairable FT (RFT). This paper deals with RFTs, including dynamic FTs. In RFTs, it is necessary to consider both the occurrence of a basic event and its disappearance. This means that the analysis of the RFT needs not only the information about whether basic/intermediate events occur, but also the one about in which states the event outputs are. This forces us into considering the state transition of a system with time domain. Markov analysis is usually adopted for the state transition analysis. The difficulty of this method is mainly due to the explosion of the number of states to be considered in the analysis. We try to handle the state transitions in the RFT analysis as equivalent event occurrences by using the concept of renewal process, and introduce a new approach to obtain the steady state top event probability. That is, the state transition of a gate output is regarded as an alternating renewal process. The renewal intensities of the process are derived applying the limit theorem of a renewal process with the up-time-ratio analysis, the mean up time and the down time analyses. Starting from the gate located at the bottom of an FT, the top event probability is calculated by a bottom up procedure.

A 62 mV 0.13 $\mu$m CMOS Standard-Cell-Based Design Technique Using Schmitt-Trigger Logic

Supply voltage reduction beyond the minimum energy per operation point is advantageous for supply voltage constrained applications, but is limited by the degradation of on-to-off current ratios with decreasing supply. In this work, we show that the effective on-to-off ratio can be considerably improved by the use of Schmitt Trigger structures, which effectively reduce the leakage from the gate output node and thereby stabilize the output level. A method for applying this concept to general logic is presented. Design rules concerning transistor sizing, gate selection and layout necessary to further minimize the required supply voltage are outlined and applied to the design of a chip implementing 8 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,\times\,$</tex> </formula> 8 bit multipliers as test structures. The only custom design step is the creation of the Schmitt Trigger standard-cell library, otherwise a regular digital tool chain is used. The multipliers exhibit full functionality down to supply voltages of 84 mV–62 mV, depending on the area overhead invested. No process or post-silicon tuning like body biasing is used. At the minimum possible supply voltage of 62 mV, a power consumption of 17.9 nW at an operation frequency of 5.2 kHz is measured for an 8 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\,\times\,$</tex></formula> 8 bit multiplier.

Simple implementation of control gate signals for the interleaved LLC resonant converter for high current application

AbstractA novel method of the gate signal generation for the interleaved LLC converter is proposed, which is based on the relationship between the output signal of a toggle flip‐flop having the double period of the input clock signal and the output gate signal of the LLC controller having almost half‐duty cycle. The gate signals for the master and slave converters are generated using the rising and falling edge instants from the original control gate signal of the controller, respectively. Therefore, the required 90° phase difference between two signals can be always kept at any instant and at any output load condition. Copyright © 2010 John Wiley &amp; Sons, Ltd.

A Novel Moment Based Framework for Accurate and Efficient Static Timing Analysis

A novel methodology for accurate and efficient static timing analysis is presented in this paper. Our methodology uses the traditional cell library table structure with one modification. The cell library tables are filled with the gate output signal moments instead of the gate output 50% delay and output slew. Using only few moments gives much better accuracy and visibility for the gate output waveform than using the time domain information. Simple convolution of the gate output moments with the interconnect moments yields the signal moments at the stage output. The parameters of the gate input signal, which are used for the table access of the successive stage, are directly computed from the predecessor stage output moments using the closed form expressions without having to explicitly transform the frequency domain moments to time domain. Thus, the interconnects and the gates are treated in a unified moment-based homogeneous framework. The proposed approach inherits the classical cell library tables approach efficiency with even reduced computation complexities. As compared to the classical cell library table approach, the proposed approach accounts for the increasingly nonlinear and non-monotonic waveform shapes which are prohibitively difficult to represent in the classical approaches. In contrary to the classical approaches, increasing the accuracy in the novel approach is made flexible and can be achieved by simply using more moments. To illustrate the concept and prove its merits, multiple examples are presented with 2-3 moments which maintain accuracy within 1%-3% as compared to SPICE.

A dynamical neural simulation mapping feature-based attention to location with non-linear cortical circuits

Visual attention mechanisms allow the visual cortex todirect cortical processing to salient locations within avisual scene, at the expense of diminished processing ofstimuli at other locations. The deployment of attentionto a given location is known as spatial attention.Attention may also be applied to a known feature in avisual scene, such as a colour or shape, enhancing itsoccurrences across the visual field. In [1], a model ofbinding distributed feature representations throughfeature-based attention predicted that attentional feed-back would act in all positions of the visual scene in lowlevel visual areas. There is now experimental evidencethat this mechanism exists [2].We present here a neural dynamical model of feature-based attention that directs attention to salient locationsinamulti-objectscenethrough interaction of stimulusdriven and cue driven neural activation. This interactionis managed by a disinhibition circuit gating output to aretinotopic neural region of the dorsal stream, thelateral intraparietal area (LIP). When visual stimuli arepresented to primary visual cortex (V1), neural activa-tion spreads into higher ventral stream areas throughincreasing neural receptive fields between layers.Stimulus driven neurons activate excitatory output andinhibitory interneuron populations in the disinhbitioncircuit. When a salient feature is cued by activation ofits associated anterior inferotemporal (AIT) neuronalpopulation, neural activity propagates to lower visualareas across all locations of the visual field. Activity inthis top-down flow inhibits the inhibitory interneuronpopulation allowing excitatory output from the disinhi-bition circuit to LIP in a retinotopic manner whereactivity is correlated in the stimulus and cue drivenpathways. In areas where the two pathways do notmatch, local inhibition in the disinhibition layer preventsneighbouring circuits’ excitatory populations from out-putting to LIP.The model exhibits effects of feature-based attention,such as the feature similarity gain principle and biasedcompetition through interactions of stimulus and cueinitiated neural activity. The dynamical nature of themodel as neural populations of Wilson-Cowan differen-tial equations allows the time-course of neural activityto be investigated.ConclusionsAlthough originally designed as a model for binding, themodel replicates the experimental correlates of feature-based attention, which strongly suggests its functionalrole is actually binding An important prediction of themodel is that local non-matches between cue andstimulus are the most important information projectedfrom the ventral to the dorsal stream and that this inter-action is highly non-linear. We present candidates forneural circuits implementing this interaction.

Effect of Rail Tapering on the Inductance Gradient Versus Armature Position by 3D-FEM

The increasing of projectile final velocity and the uniformity of current density in the special regions of the armature and rail such as the root of the armature which is in melting are some of the purposes of the railgun design. In railgun, the applied force to run an armature is resulted from the interaction of the current passing from the armature with the magnetic field in that place. Therefore, to increase the running force and gain bigger projectile velocities, we have to increase the input current or the magnetic field between two rails per a constant current. The increasing of input current can cause more heat losses in the structure of the railgun and may cause failing of the projectile procedure because of the melting of some points of the armature or rail. High magnetic fields between rails without input stimulation increasing are possible with the application of the geometrical and structural variations in rails. The current paths in rails will be closer to each other (increasing the amount of magnetic fields between them), and so, narrowing the rail using a constant current, the current density will be bigger in the cross section of the rail. We will evaluate the effect of rail narrowing in the projectile path length with consideration of a rail length of 1 m. The narrowing procedure of the rail is defined as decreasing its cross section in the projectile path length until, in the output gate, its amount reaches zero (the height of the rail is constant). The result of simulation shows that the gradient inductance will be increased with the narrowing of the cross section of the rail in the projectile path length, and this will increase the amount of the final projectile velocity.

Towards Arithmetic Circuits in Sub‐Excitable Chemical Media

AbstractA sub‐excitable Belousov–Zhabotinsky medium exhibits localized travelling excitations (in contrast to an excitable medium exhibiting target or spiral waves). Initially assymetric perturbations give birth to excitation wave‐fragments. The shape and velocity vectors of the wave‐fragments are conserved, meaning they can travel for substantial distances in the reaction media. When the wave‐fragments collide they may reflect, merge, or annihilate. We interpret wave‐fragments as values of logical variables, and the post‐collision states of the fragments as outputs of logical gates. We show how to cascade logical gates in primitive arithmetical circuits.

A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect

Gate delay evaluation is always a vital concern for high-performance digital VLSI designs. As the feature size of VLSIs decreases to the nano-meter region, the work to obtain an accurate gate delay value becomes more difficult and time consuming than ever. The conventional methods usually use iterative algorithms to ensure the accuracy of the effective capacitance Ceff, which is usually used to compute the gate delay with interconnect loads and to capture the output signal shape of the real gate response. Accordingly, the efficiency is sacrificed. In this paper, an accurate and efficient approach is proposed for gate delay estimation. With the linear relationship of gate output time points and Ceff, a polynomial approximation is used to make the nonlinear effective capacitance equation be solved without iterative method. Compared to the conventional methods, the proposed method improves the efficiency of gate delay calculation. Meanwhile, experimental results show that the proposed method is in good agreement with SPICE results and the average error is 2.8%.

Optical Digital Signal Processing in a Single SOA Without Assist Probe Light

By exploiting nonlinear effects in a single semiconductor optical amplifier, different functionalities for all-optical digital signal processing applications are implemented. In particular, we demonstrate all-optical exclusive-OR (XOR) logical operation and all-optical binary-to-quaternary ASK format conversion suitable for 2-bit all-optical digital-to-analog conversion (DAC). Both operations are performed without the use of any extra probe light beam. Beside the advantage of reduced complexity in terms of number of active elements the proposed architecture allows to preserve the input signal wavelength at the gate output and is suitable for photonic integration. Error-free operation at 10 Gb/s is demonstrated for the all-optical XOR gate, whereas correct dynamic operation, always at 10 Gb/s is observed for the binary-to-quaternary ASK format converter. Based on the proposed single semiconductor optical amplifier architecture a possible implementation of 3-bit DAC scheme with reduced number of active gates with respect to previously reported schemes is also presented.

Boolean-format biocatalytic processing of enzyme biomarkers for the diagnosis of soft tissue injury

The development of a novel enzyme logic sensing concept for the detection of soft tissue injury (STI) is reported. The new biocatalytic scheme employs creatine kinase (CK) and lactate dehydrogenase (LDH) as enzyme biomarker inputs to a biochemical cascade that mimics the operational functionality of a NAND Boolean logic gate. Under the optimal conditions, physiological and pathological levels of CK and LDH are detected optically and electrochemically by monitoring the level of reduced nicotinamide adenine dinucleotide (NADH) as an output of the logic gate. The latter technique employs a flexible carbon screen-printed electrode (SPE) to facilitate the on-site detection of STI. By establishing a pathologically meaningful threshold, relatively simple optical and amperometric assays tendered the diagnosis in a straightforward ‘True’/‘False’ digital format. Only the simultaneous presence of elevated levels of both enzyme inputs would thus trigger a positive diagnosis. Moreover, an interference investigation is performed that employs circulating levels of potential interferents. Such an enzyme cascade and enzymatically-processed biochemical information offer promise for point-of-care injury screening where a rapid determination of pathological situations is a prime consideration.

Roles of Monkey Premotor Neuron Classes in Movement Preparation and Execution

Dorsal premotor cortex (PMd) is known to be involved in the planning and execution of reaching movements. However, it is not understood how PMd plan activity-often present in the very same neurons that respond during movement-is prevented from itself producing movement. We investigated whether inhibitory interneurons might "gate" output from PMd, by maintaining high levels of inhibition during planning and reducing inhibition during execution. Recently developed methods permit distinguishing interneurons from pyramidal neurons using extracellular recordings. We extend these methods here for use with chronically implanted multi-electrode arrays. We then applied these methods to single- and multi-electrode recordings in PMd of two monkeys performing delayed-reach tasks. Responses of putative interneurons were not generally in agreement with the hypothesis that they act to gate output from the area: in particular it was not the case that interneurons tended to reduce their firing rates around the time of movement. In fact, interneurons increased their rates more than putative pyramidal neurons during both the planning and movement epochs. The two classes of neurons also differed in a number of other ways, including greater modulation across conditions for interneurons, and interneurons more frequently exhibiting increases in firing rate during movement planning and execution. These findings provide novel information about the greater responsiveness of putative PMd interneurons in motor planning and execution and suggest that we may need to consider new possibilities for how planning activity is structured such that it does not itself produce movement.

Characterization of 6H-SiC JFET Integrated Circuits over a Broad Temperature Range from -150 °C to +500 °C

The NASA Glenn Research Center has previously reported prolonged stable operation of simple prototype 6H-SiC JFET integrated circuits (logic gates and amplifier stages) for thousands of hours at +500 °C. This paper experimentally investigates the ability of these 6H-SiC JFET devices and integrated circuits to also function at cold temperatures expected to arise in some envisioned applications. Prototype logic gate ICs experimentally demonstrated good functionality down to -125 °C without changing circuit input voltages. Cascaded operation of gates at cold temperatures was verified by externally wiring gates together to form a 3-stage ring oscillator. While logic gate output voltages exhibited little change across the broad temperature range from -125 °C to +500 °C, the change in operating frequency and power consumption of these non-optimized logic gates as a function of temperature was much larger and tracked JFET channel conduction properties.

Fault Tolerant QCA Logic Design With Coupled Majority-Minority Gate

Synthesis of efficient DFT (Design for Testability) logic is of prime importance in robustly testable design of QCA based logic circuits. An ingenious universal QCA gate structure, Coupled Majority-Minority (CMVMIN) gate, realizes majority and minority functions simultaneously in its 2-outputs. This device enables area saving implementation of complex QCA logic. In the current work, we investigate cost effective DFT for QCA designs realized with CMVMIN. The fault effects at the gate outputs due to cell deposition and cell misplacement defects are characterized for concurrent testable circuit design. The effective use of unutilized outputs of CMVMIN gates, realizing a circuit, leads to the proposed fault tolerant design that may not be possible with the conventional gate structures.