Abstract
A method of synthesis of irredundant circuits of functional elements in the basis {x&y, x⊕y, 1, \(\bar x\)(y ∨ z) ∨ x(y ∼ z)} realizing arbitrary Boolean functions and admitting unit verification tests of the length not exceeding 4 is proposed in the paper for inverse or constant (stuck-at) faults at outputs of gates.
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