Output Transition Research Articles

Modeling and Mitigating Output-Dependent Modulation in Current-Steering DAC Based on Differential-Quad Switching Scheme

This brief presents a comprehensive analysis of the output-dependent modulation (ODM) in a current-steering digital-to-analog converter (CS-DAC) based on the differential-quad switching (DQS) structure. A mathematical model is proposed to accurately describe ODM, which is categorized into two types: output transition errors and boundary effect errors. A novel approach of adding isolation devices is introduced and reinterpreted to mitigate the effect of ODM. The simulation results indicate that the inclusion of isolation devices efficiently suppresses the odd harmonics at mid-to-high frequency by a value that is 13 dB lower than before. Experimental validation is conducted on a 16-bit 250 MS/s CS-DAC fabricated in a 180 nm process.

Tri-state GNRFET-based fast and energy-efficient ternary multiplier

As silicon field-effect transistors encounter increasing scaling challenges, digital system designers are shifting their attention towards multi-valued logic (MVL), specifically ternary logic. The graphene nanoribbon field-effect transistor (GNRFET) emerges as a compelling alternative among post-MOSFET technologies for the implementation of ternary logic. This paper delves into the computational intricacies of ternary logic, underscores the outstanding features of GNRFET technology, and introduces a novel GNRFET-based 1-trit ternary multiplier (TMUL) requiring only 26 transistors. The performance of the design is assessed using the Synopsis HSPICE simulator with a 32-nm GNRFET model file operating at VDD = 0.9 V. The proposed TMUL surpasses existing designs due to its efficient paths with a minimal number of transistors for each output transition, a singular power supply voltage, and an extended voltage division scheme. In comparison to other contemporary TMUL designs, the proposed design exhibits a notable enhancement, showcasing a 21.42 % reduction in delay, a 33.11 % decrease in power-delay-product (PDP), and a 58.17 % decrease in energy-delay-product (EDP). Additionally, the design is subjected to thorough testing under diverse conditions including process, voltage, temperature (PVT) fluctuations, and load variations, validating its reliability and robustness.

Research on Adaptive Cycle Engine Mode Transition Control Method

Mode transition is an important dynamic process of an adaptive cycle engine (ACE). In order to obtain a smooth mode transition process, the closed-loop controller is designed based on the strong robust augmented linear quadric regulator (ALQR) method, and with the objective of minimizing the thrust fluctuation in the process of mode transition, an open-loop geometrical mechanism control schedules optimization method based on Bézier curves is proposed, so that the closed-loop control and the open-loop control can work in coordination. The simulation results at the subsonic cruise operating point and supersonic cruise operating point show that based on the optimized open-loop geometrical mechanism control schedules and the designed closed-loop ALQR control system, the ACE achieves fast and smooth geometrical mechanisms and engine output transition during the mode transition process with a maximum thrust fluctuation of 2.58%, which is much smaller than that of the traditional linear variation geometric mechanisms with a maximum 4.64% thrust fluctuation, which verifies the effectiveness of the proposed control method.

A Family of IPT Battery Chargers With Small Clamp Coil for Configurable and Self-Sustained Battery Charging Profile

To self-sustain the constant current (CC) output to constant voltage (CV) output transition for inductive power transfer (IPT) chargers, the clamp coil assisted IPT battery chargers are better than the existing solutions due to the merits of no additional switching components, sensors, and control circuits. However, the clamp coil of these IPT chargers is bulky and hard to design, as the mutual inductances between the clamp coil and the main coupler coils are significant to the output performances. To facilitate the small clamp coil in the transmitter, this paper proposes a family of IPT battery chargers with a proper secondorder compensation network on the secondary side. The output thresholds of the IPT charger with the proper compensation can be readily configured to cope with the desired charging profile, and the clamp coil can be designed very small to decrease the corresponding cost and size. In addition, the proposed threecoil IPT charger still features automatic and smooth CC-to-CV transition to eliminate wireless communication, near unity power factor to minimize voltage-ampere (VA) ratings, soft switching to improve transfer efficiency, and open-circuit protection during CC charging. An experimental prototype of a 48 V/2.5 A battery charger is built to verify the analysis.

Robust Petri Net Controllers for Flexible Manufacturing Systems With Multitype and Multiunit Unreliable Resources

It is inevitable that resource failures occur in real production processes, and sometimes many different types of unreliable resource failures may occur. Once there are resource failures, the stagnation states of production caused by these failures, called as failure blockings (FBs), tend to appear. Hence, both deadlocks and FBs can arise to reduce production efficiency sharply. Designing robust control policies for such an automated system is thus very important. Our work focuses on a novel robust Petri net controller of flexible manufacturing systems with multitype and multiunit of unreliable resources. First, under the assumption that all resources are reliable, these systems are modeled by a class of Petri nets called systems of simple sequential processes with resources (S3PRs). For each operation place that is a holder of an unreliable resource, the corresponding repair place and related transitions are added to the net and an S3PR with unreliable resources (S3PRu) is developed. For an S3PRu, the formal definition of FBs is then proposed. Such an FB is characterized by a maximal perfect resource-transition circuit (MPC). Next, the concept of a critical set of MPCs is introduced. For any two adjacent MPCs in such a critical set, one input transition of the former and one output transition of the latter are connected by passing through resource places. A <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\xi $ </tex-math></inline-formula> -resource is a one-unit resource shared by two or more MPCs that do not contain each other. For an S3PRu without <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\xi $ </tex-math></inline-formula> -resources and critical sets of MPCs, a control place corresponding to an MPC is added to the net with its output arcs to the input transitions of the MPC. However, for an S3PRu with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\xi $ </tex-math></inline-formula> -resources or critical sets of MPCs, the output arcs of each control place are added to the source transitions of the original net. Thus, a novel robust controller of an S3PRu is synthesized. Such a robust controller can guarantee that as long as at least one unit of each type of unreliable resources can work normally, all kinds of parts can be processed to complete smoothly their tasks through any one of their process routes. Finally, three examples are provided to illustrate the efficiency of the proposed robust controller.

Study of the Frequency Self-Modulation in Gyro-TWT Based on Two -Band Amplifiers

Periodical radiation spectrum with a frequency difference of ~160 MHz is observed in hot-test experiments of Ku-band gyrotron traveling-wave tubes (gyro-TWTs). By the means of eigenmode analyses and particle-in-cell (PIC) simulation considering the whole output transition section from the interaction circuit end to the output window, we found that the circuit oscillation is pronounced because of frequency self-modulation (FSM). As a comparison, the cutoff taper contributing to the FSM is removed and a new amplifier has been developed; hot-test results indicate that the periodical property has been greatly alleviated as expected and the stability of the amplifier is well improved.

Demonstration of 4H-SiC CMOS digital IC gates based on the mainstream 6-inch wafer processing technique

In this article, the design, fabrication and characterization of silicon carbide (SiC) complementary-metal-oxide-semiconductor (CMOS)-based integrated circuits (ICs) are presented. A metal interconnect strategy is proposed to fabricate the fundamental N-channel MOS (NMOS) and P-channel MOS (PMOS) devices that are required for the CMOS circuit configuration. Based on the mainstream 6-inch SiC wafer processing technology, the simultaneous fabrication of SiC CMOS ICs and power MOSFET is realized. Fundamental gates, such as inverter and NAND gates, are fabricated and tested. The measurement results show that the inverter and NAND gates function well. The calculated low-to-high delay (low-to-high output transition) and high-to-low delay (high-to-low output transition) are 49.9 and 90 ns, respectively.

5-nm Gate-All-Around Transistor Technology With 3-D Stacked Nanosheets

A comprehensive computational study of gate-all-around (GAA) devices with 3-D stacked silicon nanosheets (also known as nanoribbons or nanowires) is presented in this article. Technology development guidelines are provided for low-power applications in 5-nm CMOS technology node and beyond. The 3-D stacked nanosheet devices lower the subthreshold swing, drain-induced barrier-lowering, and subthreshold leakage current by up to 20.75%, 38.89%, and 88.53%, respectively, when compared to a silicon-on-insulator (SOI) FinFET with 5-nm physical gate length and identical silicon area at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DD}} = {0.6}$ </tex-math></inline-formula> V and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T} = {80}\,\,^{\circ }\text{C}$ </tex-math></inline-formula> . The voltage gain of a minimum-sized CMOS inverter is increased by up to 157% with the 3-D stacked nanosheet devices, thereby providing robust operation with wider noise margins when compared to the SOI-FinFET technology. Furthermore, by scaling the supply voltage to 0.49 V, the energy consumption of a CMOS inverter is reduced by 53.81% with the GAA 3-D stacked nanosheet devices while providing similar output transition speed when compared to the SOI-FinFET technology.

A High-Voltage Fast-Speed Pulse Generator With Current-Mode Dead-Time Control Comparator for Shoot-Through Current Suppression

This letter presents a high-voltage fast-speed pulse generator with the suggested current-mode dead-time control (DTC) comparator. Measurements show that the propagation delay is in the range from 8.09ns to 14.63ns between the input pulse VIN and the output pulse VOUT and the rising and falling times of output pulses are 5.64ns and 2.86ns, respectively for 20V output pulses with the capacitive load of 22pF. The integrated wide-band I-V converter for easy monitoring of shoot-through currents reveals that shoot-through currents during high-to-low output transition can be effectively suppressed with the DTC comparator. The total power consumption of the suggested pulse generator is reduced to 154.0 mW with the DTC comparator enabled in comparison with the power consumption of 264.5 mW when the DTC comparator is disabled at the operation frequency of 7MHz with the output load of 22pF and the supply voltage of 20V.

On liveness analysis in mono-T-semiflow Petri nets based on choice-join pairs

This work introduces novel structural conditions to guarantee the liveness of Mono T-Semiflow (MTS) systems for any valid initial marking. In particular it shows that in MTS the existence of problematic choice-join pairs, a pure structural objects, is equivalent to the existence of transition firing sequences leading to deadlock markings. Moreover, such sequences always include an output transition of a choice place pc, capable of removing all the tokens from pc, but incapable of marking all the input places of a join transition tj In this situation tj will be dead, and since the net is MTS, then the net will reach a deadlock marking.

Device Parameter-Based Analytical Modeling of Power Supply Induced Jitter in CMOS Inverters

This article presents an analytical approach to determine jitter for a CMOS inverter in the presence of power supply noise (PSN). The deviation in the transition edge of the output signal from its ideal timing is modeled accurately for each transition. A power series method is used to solve differential equations for different regions of transistors during output transition. The PSN has been expressed in Taylor series expression, aids to derive closed-form equation for time interval error (TIE). The obtained results from the proposed methodology closely match with electronic design automation (EDA) simulator results and verified on 40 nm Taiwan Semiconductor Manufacturing Company (TSMC) and 28 nm United Microelectronics Corporation (UMC) foundries, demonstrating accurate modeling of jitter.

A New Linguistic Petri Net for Complex Knowledge Representation and Reasoning

Fuzzy Petri nets (FPNs) are a useful instrument for modelling expert systems to conduct knowledge representation and reasoning. Many studies have been carried out for improving the performance of FPNs in terms of their accurate representation of knowledge and power of approximate reasoning. Nevertheless, the current representation methods with FPNs are unable to handle the uncertain linguistic knowledge given by domain experts and the reliability of their judgments. In addition, the existing reasoning algorithms have no way to capture the interrelationship of the propositions with the same output transition. Therefore, we present a new type of FPNs, called 2-dimensional uncertain linguistic Petri nets (2DULPNs). The 2-dimensional uncertain linguistic variables (2DULVs) and Choquet integral are combined for knowledge representation and reasoning for the first time. The truth degrees of propositions, thresholds and certainty values of linguistic production rules are denoted as 2DULVs. Some new aggregated operators based on Choquet integral are proposed and used in the approximate reasoning to capture the interactions among antecedent propositions. Finally, an equipment fault diagnosis example is provided to illustrate the correctness and effectiveness of the proposed 2DULPN model.

Prediction of PV Output Transition by Means of Estimated Confidence Interval

In our previous study, we carried out confidence interval estimation of next‐day photovoltaic (PV) output with just‐in‐time modeling hour by hour. When the target reliability is high in particular, the width of the confidence interval becomes large certainly. Therefore, in this paper, based on behavior of the measured PV output in the morning of the targeted day, we predict of PV output transition in the estimated confidence interval in the afternoon. The proposed method, which is consistently based on black box modeling, enables us to easily and effectively narrow the confidence interval width, i.e., sharpness, of PV output. Some numerical examples, which demonstrate the effectiveness of the proposed method, are also reported. © 2020 Institute of Electrical Engineers of Japan. Published by John Wiley &amp; Sons, Inc.

Presynthesis of bounded choice-free or fork-attribution nets

A Petri net is called fork-attribution if it is choice-free (a unique output transition for each place) and join-free (a unique input place for each transition). Synthesis tries, for a given (finite) labelled transition system (LTS), to find an (unlabelled) Petri net with an isomorphic reachability graph. Synthesis often requires a large set of inequality systems to be solved, making it quite costly. In presynthesis we exploit common necessary properties of some class of Petri nets. If any of the properties do not hold, we can directly dismiss the LTS, it cannot be the reachability graph of a Petri net from our class. This also allows an implementation to give a meaningful response instead of just telling the user that some inequality system is unsolvable. If all properties hold, we may gain additional information that can simplify the inequality systems to be solved. In this paper, we enhance theoretically, and tune algorithmically a presynthesis strategy already known for choice-free nets to fork-attribution nets.

MODELING THE DYNAMIC INTERACTION PROCESSES USING OF FUZZY TIMED PETRI NETS OF TYPE VF

The dynamic interacting processes modeling is examined in the article, which shows the complex objects operation in the condition of uncertainty. A formalism intended for the development and analysis models of complex parallel and distributed systems is proposed. It is based on the mathematical apparatus of the fuzzy timed Petri nets (FTPN) of type Vf, representing generalized FTPN of type Vf , combining deterministic and non-deterministic character. The algorithm for the functioning FTPN of type Vf is developed. The proposed algorithm provides a solution to the problem of the triggering solvability of transitions occurring in conflict states, the imposition of a fuzzy structure on the network marking with fuzzy composition laws that determine the values the degrees of belonging the input and output transition positions. The model of parallel functioning processing devices is presented in the FTPN form of type Vf. An approach is proposed for modeling dynamic interacting processes based on the matrix theory of Petri nets, that provides an effective form of structure representation, model state dynamics, the space of achievable states, and triggering transitions sequence in the form of vectors and matrices set. On the example of the production model of mechanical processing, it is shown that the accepted triggering transitions rules fully show the functioning FTPN process of type Vf. As a result of the simulation, the reachability tree is obtained as a sequence of matrices.

Transition Detector-Based Radiation-Hardened Latch for Both Single- and Multiple-Node Upsets

This brief presents an output transition detector-based radiation-hardened latch (TDRHL) for reliability improvement. With an error recovery assistant logic and an in-situ transition detector, for any radiation induced single- and double-node upsets, the proposed TDRHL can 1) provide full self-recovery capability and 2) generate a warning signal for architecture-level recovery when soft errors cause the latch output flipped. The evaluation results show that TDRHL outperforms state-of-the-art double-node upset tolerant designs with addition error detection capability, and up to 5.0X power-delay-product improvement can be achieved.

Clustering of Web Application and Testing of Asynchronous Communication

In model-based testing, testing is done using Input Output Transition System (IOTS) or Finite State Machine (FSM). In synchronous testing, it is easy to know the proper sequence of input output of the system under testing, whereas, in asynchronous communication, it is tough to trace the sequences of inputs and outputs. A web application is an example of asynchronous processing, in which input/output queue management is a common issue for testing in asynchronous JavaScript and XML user interfaces. This article discusses asynchronous testing of web application by taking a Gmail account as a case study. In this article, the web application is partitioned into clusters by determining logical web pages that implement logical functions. The clusters of page objects are represented using finite state machines. From the FSMs, test scenarios are generated. The size of the test cases covering longer paths is decreased by making clusters of states. The authors conduct a queue analysis using a test architecture to investigate the behavior of the system under testing. Finally, the test cases are generated using the Selenium tool.

Event Feedback Supervision for a Class of Petri Nets With Unobservable Transitions

In this paper, we propose a method to design an on-line event feedback supervisor (EFS) for a class of Petri nets whose augmented unobservable subnets are acyclic forward synchronization and backward conflict-free (FSBCF) nets. In more detail, an FSBCF net is an ordinary Petri net in which each place has at most one output transition, and each transition has at most one input place. The designed EFS is able to compute a set of transitions that need to be forbidden based on the current observation of the system. In particular, the EFS is maximally permissive, i.e., it ensures that the controlled system never enters into illegal markings while minimally restricting its behavior. Finally, we use an example to illustrate the effectiveness of the proposed method.

An analytical comparison of optimal output transition and polynomial trajectories

This paper compares the solution of the optimal output transition approach with polynomial trajectories. Although the optimal output transition approach can guarantee the optimal output trajectory, the complex problem formulation tends to be required, especially for nonlinear systems. The aim of this paper is to investigate differences between the optimal output transition approach and the polynomial-based approach. Based on the standard first and second order linear system examples, the output transition trajectory can be obtained by using the polynomial-based approach without any significant differences when compared to the optimal output transition approach.

A B-spline-based pseudo-inversion approach for constrained optimal output transition

ABSTRACTThe contribution of this paper is to propose a new method for the continuous-time optimal output transition problem under constraints on the control effort. The new method situates in the recently proposed framework of pseudo-inversion, which proved to be very effective to achieve an almost perfect tracking. The presented method assumes a B-spline function as the external input reference r(t) forcing a given stable closed-loop system. The actual control input u(t) yielded by r(t) and forcing the plant is optimally approximated (in the least square sense) by a B-spline . The control points of the B-spline are chosen in such a way to satisfy the saturation constraints on u(t). The parameters of interest to define the solution of the considered problem are given by the control points of the B-splines r(t) and . These parameters are simultaneously estimated as elements of the vector solving the constrained least-squares minimisation of a suitably defined multi-objective cost functional. If is a sufficiently accurate approximation of u(t), the exact fulfilment of saturation constraints by is transferred to u(t). The simulations on a practical case of a relevant interest show excellent results.