Output Transition Research Articles

A Reduced Output Ringing CMOS Buffer

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> In a multichip module, the parasitic elements of the interconnections influence the performance of the devices enclosed in the package. Phenomena such as ground bounce, cross-talk, propagation delay, and over/undershoot will degrade the data signal integrity. This brief describes an output buffer structure, consisting of a double feedback loop. It reduces the oscillating behavior caused by parasitic elements in the data lines during the final phase of an output transition. The proposed structure employs simultaneous monitoring of the pad voltage and of the supplied current. Precise control of these parameters will reduce the sensitivity to reflection effects and inductive parameters of the package and printed circuit board tracks. </para>

Identificação de Sistemas a Eventos Discretos Maxplus lineares

Este artigo trata do problema de identificação de Sistemas a Eventos Discretos Max-plus lineares mono-entrada e mono-saída. O objetivo é estimar os parâmetros temporais do sistema a partir da observação dos instantes de disparo das transições de entrada e de saída, supondo que alguns parâmetros estruturais sejam conhecidos. A partir dessas condições, o método de identificação proposto é desenvolvido tendo como base o cálculo de um limitante superior para o parâmetro de temporização do ciclo. Obtém-se uma condição suficiente de excitação, relativa à variável de entrada, para a convergência do algoritmo proposto. Exemplos ilustram o método proposto.

Flatness-based optimal noncausal output transitions for constrained nonlinear systems: case study on an isothermal continuously stirred tank reactor

The issue of optimal output transition control for nonlinear differential flat systems with constraints is investigated. Of special interest is the generation of a state reference trajectory and a feedforward input, which are essential to the two-degree-of-freedom design. The proposed approach is to transfer the transition problem in the real output space into a trajectory planning issue in the flat output space. The distinguishing feature of our approach is the generation of a noncausal trajectory for the flat output. This approach is shown to be highly effective in creating performance improvements. It should also be noted that the proposed methodology guarantees that the planned trajectories are feasible for all nonlocal transitions. This allows the application of stable inversion in the planning of optimal output transitions. The proposed method is illustrated on a benchmark system, the isothermal continuous stirred tank reactor, although its applicability is much wider.

PARETO OPTIMAL FEEDFORWARD CONSTRAINED REGULATION OF MIMO LINEAR SYSTEMS

In this paper we present a methodology for the feedforward minimum-time regulation of Multiple-Input-Multiple-Output (MIMO) square linear systems. The aim is to synthesize bounded smooth input functions, subject to non-saturating constraints on the inputs and their derivatives until an arbitrary predefined order, in order to provide given transitions of the outputs. The posed problem yields to the construction of a Pareto set of output transition times, which is determined by employing an ad hoc parametrized family of output transition functions and a suitably devised input-output inversion procedure. Illustrative examples are given in order to show the effectiveness of the methodology.

Output buffer design for low noise and load adaptability

A new output buffer design for low switching noise and load adaptability is presented. Instead of using a current source, a current limiter is proposed to reduce the switching noise and static power dissipation. Output ringing is lowered by turning off the driver stage near the end of the output transition automatically. Compared with previous designs, the proposed buffer has less switching noise and improved output ringing and speed. The proposed method is simple and effective, without the necessity for a feedback control circuit.

Using stable input–output inversion for minimum-time feedforward constrained regulation of scalar systems

The paper approaches the feedforward minimum-time smooth control of non-minimum-phase linear scalar systems for set-point regulation. The aim is to synthesize a bounded input subject to non-saturating constraints on the input and its derivatives till a prespecified arbitrary order. The provided solution relies on a stable input–output dynamic inversion technique and an ad hoc parameterized family of output transition functions. The synthesized minimum-time input that exhibits pre- and post-actuation is determined by means of easily-implementable closed-form expressions. Examples are given to illustrate the methodology.

Minimum-Energy Output Transitions for Linear Discrete-Time Systems: Flexible Structure Applications

This paper finds minimum-energy inputs to change the position of an output point, on a flexible structure, from one value to another. Current methods transform the output-transition problem into a state-to-state transition problem by constraining the initial and final states of the output transition, for example, to be rest (rigid-body) configurations of the flexible structure. However, the choice of the initial and final states can be ad hoc, and the resulting output-transition cost (input energy) might not be minimum. The contribution of this paper is the direct solution of the optimal output-transition problem; the problem is posed and solved for general linear discrete-time systems. The novelty of the proposed approach is that inputs are not applied just during the output-transition time interval; rather, inputs are also applied outside the output-transition time interval, that is, before the beginning of and after the end of the output-transition time interval. (These inputs are called pre- and postactuation.) The implications of using pre- and postactuation are illustrated by using an example of discrete-time flexible structure model, which consists of a flexible rod connecting two masses. Simulation results are presented, which show substantial reduction of output-transition costs with the use of the proposed method when compared to the use of the standard state-to-state transition approach.

A new design for a PID plus feedforward controller

In this paper, a new design and tuning procedure for a PID plus feedforward controller is proposed. It consists of determining a feedforward signal in order to achieve a predefined process output transition time assuming a first order plus dead time model of the process. Then, the PID parameters are tuned by any conventional method in order to assure a good load disturbance rejection and the reference signal to the closed-loop system is obtained by filtering appropriately the set-point step signal. Simulation and experimental results show that the method outperforms the typical (inverse) model-based approach despite its simplicity and it is therefore suitable to implement in Distributed Control Systems as well as in single-station controllers.

IMPROVED PI CONTROL VIA DYNAMIC INVERSION

In this paper we present a new design methodology to achieve high performances in the set point following task by means of a standard Proportional-Integral (PI) controller. In particular, a dynamic inversion procedure is adopted to synthesize a suitable command input to the closed-loop control system. In this way, the PI parameters can be selected for a load rejection purpose, as the designed command input is capable to ensure in any case that a desired output transition is accomplished with a low rise time and a small overshoot. A salient feature of the technique is that it does not require a complex identification phase, as a simple first-order plus time delay (FOPTD) model of the process, which can be easily obtained by means of an open-loop step response, suffices. A Padé approximation is then adopted to deal with time delays. Illustrative examples show the effectiveness of the method, which preserves all the basic characteristics of the PI controllers and it is therefore suitable to be applied in an industrial environment.

Propagation delay and short-circuit power dissipation modeling of the CMOS inverter

This paper introduces a new, accurate analytical model for the evaluation of the delay and the short-circuit power dissipation of the CMOS inverter. Following a detailed analysis of the inverter operation, accurate expressions for the output response to an input ramp are derived. Based on this analysis improved analytical formulae for the calculation of the propagation delay and short-circuit power dissipation, are produced. Analytical expressions for all inverter operation regions and input waveform slopes are derived, which take into account the influences of the short-circuit current during switching, and the gate-to-drain coupling capacitance. The effective output transition time of the inverter is determined in order to map the real output voltage waveform to a ramp waveform for the model to be applicable in an inverter chain. The final results are in very good agreement with SPICE simulations.

Effect of the Transition Region on Wavelength Sensitivity of Directional Coupler Switches

The effect of the coupling in the input and output transition regions is considered in this analysis. Based on the numerical results, some salient features of the dispersively induced crosstalk of directional coupler switches are demonstrated and discussed in detail. More extensive studies are given to evaluate the effect of the coupler parameters on wavelenght sensitivity of directional coupler switches and to establish useful guidelines for design of the switches.

Modelling output waveform and propagation delay of a CMOS inverter in the submicron range

An accurate, analytical model is presented for the evaluation of the CMOS inverter delay in the submicron regime. Following an exhaustive analysis of the inverter operation, accurate expressions of the output response to an input ramp are derived, which result in the analytical calculation of the propagation delay. These expressions are valid for all the inverter operation regions and input waveform slopes, and take into account the influences of the short-circuit current and the gate–drain coupling capacitance. The effective output transition time of the inverter is determined, in order to map the real output waveform to a ramp waveform for the model to be applicable to CMOS gate chains. The results are in very good agreement with SPICE simulations.

Effects of simultaneous switching noise on the tapered buffer design

Complementary metal-oxide-semiconductor (CMOS) output buffers, comprised of a series of tapered inverters, are used to drive large off-chip capacitances. The ratio of the size of transistors between two consecutive stages is the buffer taper factor. With higher frequency of operation and simultaneous switching of the output drivers, the parasitic inductance present at the pin-pad-package interface results in significant switching noise on the power lines. A comprehensive analysis and estimate of simultaneous switching noise (SSN) including the velocity saturation effects seen in the submicron transistors during the switching of output drivers is presented. The effect of SSN on the overall buffer propagation delay and transition time is discussed. The presence of SSN results in an increase in the optimum taper factor between inverter stages for a given capacitive load. Beyond a critical value, the output transition time of a tapered buffer increases with reducing taper factor due to SSN. SSN can be reduced by skewing the switching of output buffers, SPICE simulation results show that skewing buffer switching with additional inverter stages reduces SSN and increases buffer propagation delay.

Feedback Controller Design in Max-Algebra

For timed event graphs, linear models are obtained by using Max Algebra. This paper describes a method to control such graphs in the SISO case (one input transition and one output transition). After defining the optimal tracking problem, we introduce a feedback control structure and present its practical implementation. Illustrative examples are provided.

The design of low jitter hard limiters

Hard limiters, which are nearly identical to level crossing detectors or zero crossing detectors, are an integral part of many communications systems, of devices for characterizing precision oscillators, and of analog-to-digital converters. The purpose of a hard limiter is to divide the continuous range of an analog input signal into two regions and to provide a digital output indicating the region in which the signal is. This digital output must, by definition, have an extremely short transition time. A hard limiter is thus a slope amplifier, since a slowly varying input must produce a very rapidly varying output. Noise in the amplifiers causes the output transition to be jarred from its correct position producing jitter in the output. This paper presents the analysis and details the design of very low jitter hard limiters. Their immediate application is to the measurement of high stability signal sources and to deep space communication and ranging; the results, however, are easily adapted to many other purposes such as waveform digitization. One of the devices described has been built. Its performance agrees closely with theory and is vastly superior to that of conventional instrumentation.

Split inherent-capacitive load model for CMOS buffer design

CMOS buffers are made up of a series of tapered inverters with each inverter driving a larger inverter. A split inherent-capacitance load model has been used in the design of tapered buffers, giving an improved value for the optimum taper factor between inverter stages. The overall buffer propagation delay and output transition time so obtained are smaller than those obtained using the split-capacitive load buffer model, but there is a small increase in area and power dissipation.

Delay-Macromodelling Of Cmos Transmission-Gate-Based-Circuits

Transmission gates are used extensively in CMOS VLSI circuits. However, very few delay models have been developed for transmission gates or transmission-gate-based circuits. Accurate delay models are presented in this paper and compared with delays obtained from SPICE simulations. These delay models are based on analytical expressions for the output voltage of the transmission-gate-based circuits in various regions of operation obtained from the mode of operation of MOS transistors that make up the circuit. The model-based output propagation delays and transition times are within 10% of SPICE-simulation-based delays for various capacitive loads and input transition times.

High-speed, low-switching noise CMOS memory data output buffer

This paper describes a data output buffer for highspeed CMOS integrated memories with a high data output pin count. The buffer minimizes the switching noise induced on supply lines while achieving very fast output transitions by combining output presetting techniques together with adequate driving of the output pull-up and pull-down transistors. Tristate operation and zero static power consumption are also provided. The buffer was integrated in a 16-Mb EPROM device. It occupies 0.06 mm/sup 2/ and ensures a better than 15 ns output transition time with a load capacitor of 100 pF. >

Comments on the optimum CMOS tapered buffer problem

Two recent papers, one by Li et al. (see ibid., vol 25, p1005-8,1990) and the other by Prunty and Gal (see ibid., vol. 27, no. 1, p118-9,1992), on the optimum CMOS tapered buffer problem are commented on. These papers claim that an equivalent "short-circuit" current capacitance should be added to the output capacitance of an inverter to account for the increased propagation delay obtained because of the short-circuit current that flows when a real input waveform is considered instead of an input step voltage. The reasoning results in an optimum tapering factor that is dependent on the waveform rise and fall times. However, the propagation delay only depends on the load capacitance and the ratio of the input to output transition times. In a fixed-taper buffer these transition times are equal making the optimum tapering factor independent of the "short-circuit" current. The comments also suggest an improved method of determining the optimum tapering factor in practical situations based on circuit simulations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Multiple-Weighted Marked Graphs

Theory regarding marked graphs is not applicable when concurrent systems must be constructed as a petri net in which each place has exactly one input and output transition and there exist multiple arcs between a place and a transition. Many parallel programs and manufacturing systems capable of bulk production can be modeled as such multiple-weighted marked graphs, called WMGs for short. Motivated by the practical need in analyzing their performance, this paper presents the conditions under which a WMG can be evaluated. An application to a parallel computer system is also given