Output Ripple Research Articles

Fixed-Time Backstepping Sliding-Mode Control for Interleaved Boost Converter in DC Microgrids

Interleaved boost converters (IBCs) are commonly used as interface converters for DC microgrids (MGs) due to their high efficiency and low output ripple. However, the MGs system can easily become unstable due to the negative impedance characteristics of constant power load (CPL) and rapid power fluctuations. This paper proposes a fixed-time backstepping sliding-mode controller (FTBSMC) aimed at stabilizing the MGs system and achieving fixed-time tracking of the DC bus voltage. Firstly, the fixed-time disturbance observer (FxTDO) estimates the load disturbance at a fixed time, which improves the fast disturbance resistance of the system. Then, based on the dis-turbance estimation, the FTBSMC is designed, which combines the fast dynamic response of the sliding-mode control with the global stability of the backstepping control, avoiding the singularity problem of the conventional sliding-mode control. In addition, a first-order nonlinear filter is employed to avoid the direct differentiation of conventional backstepping control and at the same time to ensure global fixed-time stability. The fixed-time convergence of the proposed FTBSMC is rigorously demonstrated by using Lyapunov stability analysis. Finally, the FTBSMC proposed is verified by simulation and experiment in terms of faster dynamic response and stronger robustness.

Addressing output ripples in low-power CMOS-based multistage DC-DC boost converters for self-powered electrochemical sensors applications

In modern electronic systems, the DC-DC converter plays a pivotal role by facilitating the conversion of direct current (DC) from one voltage level to another. Given the diverse voltage requirements of contemporary chips, a single chip may encompass multiple circuitry groupings, each necessitating specific voltage levels for optimal functionality. To address this need, voltage converters are essential, whether it involves increasing the voltage (Boost converter), decreasing the voltage level (Buck converter), or performing both functions (Buck-boost converter). This paper presents a novel multistage DC-DC converter designed to minimize voltage ripples. The proposed three-stage DC-DC converter is supplied with a 1.5-V input and achieves a four-boost ratio. The cascaded architecture integrates switching capacitors and a gyrator, complemented by a terminating low-pass filter, resulting in a minimal voltage ripple of 0.0003 % relative to the maximum output voltage. Notably, integrating the gyrator enables an inductorless CMOS-based architecture, significantly reducing layout area to 30 × 140 μm2. Furthermore, the converter's transient response was simulated, yielding a response time of 90 ms.

Power factor preregulation in power supplies using modified single stage non-isolated interleaved Sepic converter with minimal part count

This paper pontificates on design and realization of low-cost single phase single stage modified interleaved Sepic (MILS) converter for power supplies. On contrary to the classical Sepic power converters, the introduced active power factor correction (APFC) converter involves simple idea of paralleling that enables low input and output ripples with minimal device count. The interleaving conceptualization also lessens current stresses and static losses. Also, this modified power processing converter reveals natural power factor correction (PFC) and zero current switching (ZCS) features by discontinuous conduction mode (DCM) operation. Furthermore, the practical corroboration of the proposed converter is built and tested for 250 W hardware model to affirm benefits with 92 % efficiency and their relevant outcomes are reported in this scope. Finally, the power quality (PQ) attributes like, input power factor (PF), total harmonic distortion (THD) over input current under stable and transient cases are disclosed to prove bettered PQ limits at the AC mains as prescribed by various IEEE-519 and IEC 61,000–3-2 standards.

A low-noise multipath operational amplifier with Gm-shared ping-pong and ripple averaging techniques

This paper presents a low-noise chopper-stabilized multipath operational amplifier with transconductance (Gm) sharing technique between ping-pong stages and ripple averaging technique. While the chopper stabilization is effective in reducing low-frequency noise and offset, output signals may yet contain ripples caused by the modulated amplifier offset. Several schemes can be implemented to suppress these output ripples; however, they require additional chip area and current consumption. The proposed ripple averaging technique effectively eliminates chopper ripples with very low additional power consumption of switched capacitors. To reduce the power consumption and circuit area, the Gm-shared ping-pong scheme is also proposed. The proposed circuit was implemented using a 0.18-μm CMOS process, with a total current consumption of 121.91 μA, and a supply voltage of 1.8 V. It occupies a chip area of 0.33 mm2 and exhibits an input-referred offset of 4.833 μV with a standard deviation 0.861 μV. The proposed amplifier has the input-referred noise level of 20.1 nV/√Hz.

A 1.87 µW Capacitively Coupled Chopper Instrumentation Amplifier with a 0.36 mV Output Ripple and a 1.8 GΩ Input Impedance for Biomedical Recording

Chopper and capacitively coupled techniques are employed in instrumentation amplifiers to create capacitively coupled chopper instrumentation amplifiers (CCIAs) that obtain a high noise power efficiency. However, the CCIA has some disadvantages due to the chopper technique, namely chopper ripple and a low input impedance. The amplifier can easily saturate due to the chopper ripple of the CCIA, especially in extremely low noise problems. Therefore, ripple attenuation is required when designing CCIAs. To record biomedical information, a CCIA with a low power consumption and a low noise, low output ripple, and high input impedance (Zin) is presented in this paper. By introducing a ripple attenuation loop (RAL) including the chopping offset amplifier and a low pass filter, the chopping ripple can be reduced to 0.36 mV. To increase the Zin of the CCIA up to 1.8 GΩ, an impedance boost loop (IBL) is added. By using 180 nm CMOS technology, the 0.123 mm2 CCIA consumes 1.87 µW at a supply voltage of 1 V. According to the simulation results using Cadance, the proposed CCIA architecture achieves a noise floor of 136 nV/√Hz, an input-referred noise (IRN) of 2.16 µVrms, a closed-loop gain of 40 dB, a power supply rejection ratio (PSRR) of 108.6 dB, and a common-mode rejection ratio (CMRR) of 118.7 dB. The proposed CCIA is a helpful method for monitoring neural potentials.

A parameter design method of LC filter circuit for closed‐loop dynamic power supply system based on linear power amplifier

AbstractThe linear power amplifier (LPA) suffers from low power supply utilization in the DC power supply mode, leading to reduced output efficiency. This paper constructs an efficient power supply mode based on closed‐loop dynamic power supply system (CLDPSs). The CLDPSs can generate a pair of bipolar dynamic power supplies based on a predetermined signal to provide power to LPA, which can maintain a small voltage drop between the power supply and the output of LPA, thereby improving the power supply utilization of LPA. In addition, the study also focuses on the conflicting relationship between the output ripple and the dynamic performance of the CLDPSs, for which a new parametric design of the LC filter circuit is proposed, aiming to achieve a balance between these two aspects. Finally, a voice coil motor driving platform is constructed for experimental testing. The results demonstrate that the output ripple and dynamic performance of the CLDPSs can be balanced. In comparison to the DC power supply mode, the CLDPSs power supply mode can enhance the efficiency of LPA by 2 times while the driving accuracy of voice coil motor is basically unchanged.

Analysis of the effect of mutual inductance on reducing output current ripple of the modified DC-DC Cuk converter

DC-DC converters exhibiting minimal input and output ripple are extensively employed across a diverse range of applications. This paper presents a proposed modification to the DC-DC Cuk converter. The converter is developed by modifying a conventional Cuk DC-DC converter to exhibit boost characteristics. The DC-DC converters possess the capability to function as versatile units that can be employed in a multitude of applications, ranging from DC-DC conversion to DC-AC conversion (inversion). This paper presents a novel DC-DC converter design that aims to achieve reduced ripple in both input and output currents. By employing the principle of mutual inductance, it is possible to further mitigate the presence of ripple current. The analysis of the impact of mutual inductance on the output voltage and ripple current of the proposed converter has been conducted. The validity of the derived analytical method has been confirmed through both simulated and experimental investigations. The utilization of mutual inductance in the proposed modified Cuk converter has been demonstrated to result in reduced current ripple.

Low-power DC-DC converters for smart and environmentally-friendly electric vehicles: design, simulation, and fabrication on a glass substrate

This research focuses on evaluating and comparing different DC-DC converter designs, specifically for low power applications. The study considers inductor-based, switching capacitor, and linear voltage regulator (LVR) DC-DC converters. While there has been critical investigation of DC-DC converters in the literature, there is a gap in assessing their performance based on a comprehensive set of conflicting parameters. Additionally, there is a lack of research on matching the most suitable DC-DC converter with specific low power applications. The chosen application for this study is a DC-DC converter on a glass substrate, specifically for smart glass in electric vehicles. The research presents a complete process that includes design, simulation, layout, fabrication, and measurement. Through simulations, a 4.8 V to 3.3 V buck converter is recommended, demonstrating an almost ideal response time and minimal output ripples. Experimental measurements also confirm a low output ripple of 0.3 %. By addressing this research gap and providing a comprehensive evaluation of DC-DC converters, this study contributes to the development of efficient and reliable power solutions for smart glass applications in electric vehicles.

87‐2: Modeling and Simulation for Mitigating Display Noise Caused by PMIC Ripple

The output ripple of the Power Management IC (PMIC) is one of the causes of display panel noise. This paper introduces modeling and simulation methods aimed at predicting and mitigating noise induced by PMIC ripple. If the display panel simulation is performed using an ideal voltage source, the ripple characteristics of the PMIC cannot be included. The improved method accurately predicted the ripple of the voltage input to the panel by modeling flicker noise and thermal noise, which are the main causes of PMIC noise, and modeling the Z‐parameter and decoupling capacitor of the PCB. In addition, it was possible to minimize ripples and finally reduce display noise by optimizing the design of the power supply circuit.

A Spread-Spectrum Modulation Scheme for a 3 × 6 Indirect Matrix Converter Based on a Current Ripple Model

Focused on addressing harmonic suppression in multiphase indirect matrix converters (IMCs), this study explores spread-spectrum modulation technology through ripple analysis calculations. We introduce a current ripple spread-spectrum modulation (CR-SSM) method tailored for multiphase IMC systems. In this approach, a 3 × 6-phase IMC is modeled as a two-port network, and a small-signal model of the output side is established. The transfer function is utilized to analyze the two-port network in the complex frequency domain (s-plane). The time-domain expression of the output current ripple is derived in vector form. Subsequently, the distribution of the output ripple and locus are determined based on specified constraints. The carrier frequency is dynamically adjusted online according to the specified ripple locus. Compared to classical periodic PWM methods, this approach offers a broader range of frequency variations and achieves a more uniform output spectrum. Furthermore, CR-SSM optimizes system efficiency and enhances spread-spectrum modulation. Experimental results demonstrate that this method effectively enhances the quality of input and output waveforms in multiphase IMC systems.

A fast-response RBCOT buck converter with second-order differential and integrator compensation based on FVF

A second-order differential and integration circuit based on a flipped voltage follower (SDI-FVF) is proposed in the paper, providing compensation ripple for the buck convert with ripple-based constant on-time (RBCOT). Additionally, an adaptive conduction time module is designed which stabilizes the operating frequency of the converter in continuous conduction mode (CCM) and guarantees stable conduction time in discontinuous conduction mode (DCM). The proposed RBCOT buck convert has been designed using 180 nm process. It operates with an input voltage range of 2.5 V–5 V and an output voltage range of 0.8 V–5 V, accommodating a load current range of 0 A to 3 A. It operates at a frequency of 4 MHz, exhibiting an output ripple of 1.4 mV, achieving a peak efficiency of 91.5 %. The efficiency exceeds 85 % under a load current of 1 mA. The undershoot and overshoot voltage are only 0.13 mV and 7.1 mV with a load current variation rate of 3 A/μs.

Chaos control of Superbuck converter based on resonant parametric perturbation method

As a current control method, valley current mode (VCM) control is widely applied in DC-DC converters due to its absence of dead time restrictions and excellent transient response performance. This paper constructs a discrete iterative model of the VCM-controlled Superbuck converter. The bifurcation diagram is employed to analyze the impact of the reference current variation on the converter, and further validation is conducted through phase portraits and Poincaré sections. By introducing the resonant parametric perturbation method, a small perturbation signal is applied to the reference current to achieve chaos control. Simulation results demonstrate that this method effectively suppresses the chaotic behaviour of the Superbuck converter with the variation of reference current, significantly improving the performance and output ripple of the converter.

Research on Maximum Power Control of Direct-Drive Wave Power Generation Device Based on BP Neural Network PID Method

Ocean wave energy is a new type of clean energy. To improve the power generation and wave energy conversion efficiency of the direct-drive wave power generation system, by addressing the issue of large output errors and poor system stability commonly associated with the currently used PID (proportional, integral, and derivative) control methods, this paper proposes a maximum power control method based on BP (back propagation) neural network PID control. Combined with Kalman filtering, this method not only achieves maximum power tracking but also reduces output ripple and tracking error, thereby enhancing the system’s control quality. This study uses a permanent magnet linear generator as the power generation device, establishes a system dynamics model, and predicts the main frequency of irregular waves through the Fast Fourier Transform method. It designs a desired current tracking curve that meets the maximum power strategy. On this basis, a comparative analysis of the control accuracy and stability of three control methods is conducted. The simulation results show that the BP neural network PID control method improves power generation and exhibits better accuracy and stability.

The Study of Multi-Terminal DC Systems in an Offshore Wind Environment: A Focus on Cable Ripple Analysis

This paper studies the THD and AC losses on the DC cables of offshore wind farm-based multi-terminal HVDC systems when they extract and deliver power from and to more than one connection point. In the paper, the study of a full system PLECS + Simulink model with two branches, including a wind resource, a wind turbine, a Permanent Magnet Synchronous Generator (PMSG), a Pulse Width Modulation (PWM) rectifier, a Single Active Bridge (SAB) DC–DC converter, an Input Parallel Output Series (IPOS) DC–DC converter, HVDC cables, and a simplified onshore system, is presented. It focuses on the investigation of the output ripple content of multiple DC–DC converters on DC cables under different wind conditions with different voltage and power ratings. The importance of the study is providing a general understanding of the operation of the innovative offshore wind farm-based DC system, as well as the interaction between different DC–DC converters and their influence on cable ripple content under different situations.

A DC-DC Converter with Switched-Capacitor Delay Deadtime Controller and Enhanced Unbalanced-Input Pair Zero-Current Detector to Boost Power Efficiency

This proposed work introduces a DC-DC converter with Switched-Capacitor Delay Deadtime Controller (SCD-DTC), Digitally Controlled Start-Up Block (DC-SUB), and Enhanced Unbalanced-Input Pair Zero-Current Detector (EUIP-ZCD) that helps to improve the overall power efficiency. It also introduces the discussion of key signal waveforms and the two major optimization flowcharts. This proposed DC-DC converter can simultaneously achieve optimized deadtime (body diode conduction < 3 ns) and almost fully eliminate the phenomenon of reverse inductor current (RIC). Furthermore, it also shows that it can achieve a well-regulated output voltage of 1.8 V with <0.01% of output ripple riding on it. All the post-layout simulation results are carried out using 0.18 µm 1P6M CMOS process using Cadence Virtuoso Spectre Circuit Simulator. The silicon chip area of our proposed work (including the output pad frame) is 1.44 mm2. The chip fabrication was sent out in January 2024 and the return of the measurement dies is expected in March 2024. The post-layout simulation results will no doubt closely resemble the measurement results since the proposed work is mostly controlled by digital blocks.

DC Output Ripple Suppression of High-Frequency DC–DC Resonant Converter

DC Output Ripple Suppression of High-Frequency DC–DC Resonant Converter

Optimized Maximum Power Point Tracking using Giza Pyramid Construction Algorithm for Photovoltaic Systems

Background: One of the key challenges in maximizing the performance of PV systems is the efficient tracking of the maximum power point (MPP) under varying operational conditions, including changes in solar irradiance and temperature. Accurate MPP tracking is essential for achieving optimal energy conversion efficiency and maximizing the electricity generation potential of the PV array, even during partial shading conditions. Traditional maximum power point tracking (MPPT) algorithms, such as the incremental conductance (INC) method, often struggle to efficiently handle partial shading conditions. As a result, there is a need for more sophisticated and robust optimization techniques that can effectively address this challenge. This study presents a novel and innovative Giza Pyramid Construction (GPC) algorithm to solve the partial shadinginduced MPP tracking problem. Objective: This study aims to apply the Giza Pyramid Construction (GPC) algorithm for optimized maximum power point tracking in photovoltaic systems under partial shading conditions, aiming to enhance energy conversion efficiency and overall system performance. Methods: The methodology involves implementing the Giza Pyramid Construction (GPC) algorithm as the core optimization technique for maximum power point tracking (MPPT) in photovoltaic (PV) systems. The GPC algorithms are utilized to iteratively adjust the duty cycle of the boost converter, enabling efficient power extraction from the PV array under varying shading conditions. The performance of the GPC algorithm is evaluated through simulations in MATLAB/SIMULINK and compared against conventional MPPT methods like INC and DGO techniques. Results: The successful application of the Giza Pyramid Construction (GPC) algorithm for optimized maximum power point tracking in PV systems under partial shading led to significantly reduced optimization time, faster settling times, and minimized output ripples. With the proposed GPC MPPT, optimization time is reduced to 41ms, settling time is reduced to 93ms, and ripples are minimized to 0.092%. Conclusion: the Giza Pyramid Construction (GPC) algorithm demonstrates its effectiveness as a robust and efficient maximum power point tracking method in photovoltaic systems, particularly under partial shading conditions. The improved optimization speed, reduced settling times, and minimized output ripples underscore the GPC algorithm's potential to enhance the overall efficiency and reliability of PV systems, paving the way for its practical implementation in real-world renewable energy applications.

Capacitorless DC-DC Regulator as a Candidate Topology for Photovoltaic Solar Facilities

Linear-assisted DC/DC converters (or linear-switching hybrid DC/DC converters) consist of a voltage linear regulator (classic NPN or nMOS topologies and LDO) connected in parallel with a switching DC/DC converter. They are a good candidate for energy processing in photovoltaic solar facilities. In order to control these hybrid structures, different strategies exist, allowing fixing the switching frequency as a function of some parameters of the linear regulator. This article compares two control strategies that, although can be applied to the same circuital structure of linear-assisted converter, are sensibly different. The first one, reported in previous literature, cancels completely the average current through the linear regulator in steady state to achieve a reduction of the losses. Thus the efficiency of the whole system increases and almost equals the one of the standalone switching converter. The proposed approach, in spite of a slightly increment of linear regulator’s losses, reduces the output ripple due to the crossover distortion of linear regulator output stage.

Evaluation of PV-based Buck-Boost and SEPIC Converters for EV Charging Applications

In recent decades, environmental issues have become an area of greatest concern due to changes in global climate conditions. The transportation sector is a major contributor to carbon dioxide emissions, accounting for more than 22.9% of total carbon dioxide emissions. At present, most vehicles run on gasoline/diesel as fuel which is unsustainable and unviable as fossil fuels produce carbon emissions and fuel costs are rising. To address these issues, electric vehicles (EVs) offer an attractive solution as alternative to internal combustion engine vehicles that use electricity as an energy source. It is logical to use renewable energy to charge vehicles, which makes renewable energy an end-to-end clean energy source. In electric vehicles, energy conversion plays an important role. In the energy conversion process, alternating current (AC) can be converted to direct current (DC), or direct current can be converted to alternating current. In EV fast charging applications, DC-to-DC conversion is used, which requires DC-to-DC converters. In this paper, a detailed evaluation of the Buck-Boost and Single-Ended Primary Inductance Converters (SEPIC) with PV as input is analyzed for EV charging applications to make it end-to-end clean energy. For this purpose, a 5-by-5 PV system with a Buck-Boost, SEPIC converters with particle swarm optimization technique is considered, which is simulated in a MATLAB/SIMULINK environment. The simulation results showed that the ripples in output are minimal in SEPIC which supports the smooth and efficient charging of EV battery.

A 33V to 1V Ripple-Less Buck Converter With the Inverted AC Current Replica Circuit and Sub-0.5% Output Ripple for 5G Low Earth Orbit Application

A 33V to 1V Ripple-Less Buck Converter With the Inverted AC Current Replica Circuit and Sub-0.5% Output Ripple for 5G Low Earth Orbit Application