Output Ripple Research Articles

Harmonic Resonance Suppression Strategy of the Front-End Vienna Rectifier in EV Charging Piles

Owing to the distributed installation position, the electric vehicle (EV) charging pile is usually connected to the grid via transmission cables of different lengths. The resonance of parasitic inductance and parasitic capacitance on the transmission cables might amplify the background harmonics, which result in a serious distortion of the grid-connected current of the front-end Vienna rectifier of EV charging piles. To overcome the resonance issue, this article proposes a harmonic resonance suppression strategy of the Vienna rectifier, which reshapes the closed-loop input harmonic impedance of the Vienna rectifier to be close to the characteristic impedance of the transmission cable by optimizing the traditional dual closed-loop control strategy of the Vienna rectifier based on the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dq</i> coordinate frame. The proposed suppression strategy can not only ensure the low ripple output voltage of the Vienna rectifier, but also suppress the background harmonic resonance amplification; thus, the power quality of the Vienna rectifier grid-connected current and the voltage at the point of common coupling will be improved effectively. Both the simulation and experimental results verify the effectiveness and correctness of the proposed strategy.

Novel Soft-Switched Three-Phase Inverter With Output Current Ripple Cancellation

A novel three-phase dc–ac full-bridge soft-switched inverter topology is proposed in this article that provides an ultralow ripple output current. The proposed circuit utilizes a passive filter that comprises a transformer, an inductor, and a capacitor for achieving soft switching and output current ripple cancellation. Zero-voltage switching (ZVS) is achieved at turn <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> time instant for all the switches in the proposed circuit. The magnitude of ZVS current is optimized throughout the line cycle by the application of the variable frequency modulation technique. In addition to soft switching, an ultralow ripple output current is achieved due to the current ripple cancellation property of the proposed circuit. The output current ripple cancellation is achieved by combining the inverter current with an additional high-frequency ripple current generated by the passive filter. The soft-switched inverter operation and inherent current ripple cancellation achieved by the proposed circuit, result in a high power conversion efficiency. Theoretical analysis and the improvements in inverter performance presented in this article are validated through the experimental verification of the proposed converter topology using a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mathbf{600\text{-}W}$</tex-math></inline-formula> lab prototype.

Fuzzy Based Interleaved Step-up Converter for Electric Vehicle

This work focuses on the fuzzy controller for the proposed three-phase interleaved Step-up converter (ISC). The fuzzy controller for the proposed ISC converters for electric vehicles has been discussed in detail. The proposed ISC direct current (DC-DC) converter could also be used in automobiles, satellites, industries, and propulsion. To enhance voltage gain, the proposed ISC Converter combines boost converter and interleaved converter (IC). This design also reduces the number of switches. As a result, ISC converter switching losses are reduced. The proposed ISC Converter topology can produce a 143 V output voltage and 1 kW of power. Due to the high voltage gain of this converter design, it is suitable for medium and high-power systems. The proposed ISC Converter topology is simulated in MATLAB/Simulink. The simulated output displays a high output voltage. But the output voltage contains maximum ripples. Fuzzy proposes an ISC Converter which makes closed loop responsiveness and reduces the output voltage ripple. The proposed ISC converter has the lowest ripple output voltage, which is less than 2%, because the duty cycle is regulated using the fuzzy logic controller. It offers high voltage gain, minimal ripple, and low switching loss. The performance of the proposed converter is compared to that of the fuzzy and Proportional Integral (PI) controllers implemented in MATLAB.

A CMOS Dual-mode DC-DC Converter with a Digital Dual-mode Controller

This paper describes a CMOS dual-mode DC-DC converter with a digital mode controller, which includes PFM controller and PWM controller. The proposed dual mode controller employs 3-bit control circuit to select a number of counts from a 5-bit digital counter, so that the 3-bit control circuit is capable of adjusting the transient boundary load current between PFM mode and PWM mode. The proposed dual-mode DC-DC converter with a digital dual-mode controller was implemented with a 180 nm 1P/6M BCDMOS process. The measurement results demonstrated the wide range of the input voltage from 2.2 V to 5.0 V with a fixed output voltage of 1.2 V with 3-bit digital capability to control boundary current between PFM mode and PWM mode. The proposed DC-DC converter achieved the peak PFM and PWM power efficiencies of 85% and 91 %, respectively, with an output ripple voltage of 12-32 mV at a switching frequency range of 60 kHz to 2.3 MHz and a load current range of 10 mA to 500 mA.

Integrated 0.35-µm CMOS Control Circuits for High-Performance Voltage Mode DC–DC Boost Converter

The integrated DC–DC converter is appropriate for use in many domains, namely, display, cellular, and portable applications. This paper presents an integrated control circuit for a monolithic voltage mode DC–DC boost converter for display driver applications. The control circuits consist of a transconductance amplifier, a comparator, and an oscillator. The boost converter consists of an inductor, two MOSFET, and an output RC filter. The control circuits are designed for fast transient response and low output ripple. The transconductance amplifier, comparator, and oscillator in the control circuit are designed to operate at a supply voltage of 3.3 V and an operating frequency of 5.5 MHz. The transconductance amplifier consists of an operational amplifier and an RC filter in the feedback path. The RC filter has a pole with a sufficient phase margin for high stability. The control circuits are realized in a 0.35-μm CMOS process together with the DC–DC converter. The fabricated DC–DC converter was evaluated by experiment and simulation. Testing of the proposed control circuits shows that the output transient time can be controlled within 7 μs, and the output voltage is accurately controlled with a ripple ratio of 3%.

Ripple-Free Multiphase Interleaved Stacked Converter for High-Power Applications

A novel control technique that guarantees a ripple-free output current and voltage of a dc–dc multiphase staked interleaved converter is proposed. The conventional multiphase interleaved converters have been extensively used in various applications. However, ripple cancellation in these converters solely depends on the number of phases and can only be achieved at specific duty cycles. On the other hand, wide-range and ripple-free output are important paramount features for many modern applications. Therefore, the presented converter aims to combine the advantages of both the multiphase interleaved and the stacked converters into a single-unit converter suitable for high-power applications. Ripple-free output current/voltage is always guaranteed regardless of the number of phases and duty cycle values. This feature is accomplished by adding a fractionally-rated phase-leg to the conventional multiphase interleaved converter and modulating it with the proposed control approach. The configurable logic block, a state-of-the-art tool developed by Texas Instruments, is utilized to reduce the hardware size of the entire conversion system while increasing its speed and flexibility. Extensive simulation studies are carried out to confirm the functionality of the proposed control scheme. A laboratory porotype is developed to validate the effectiveness of the proposed control method experimentally. With only a few more components, significant reductions in output ripples are achieved.

A Fully Integrated Multi-Phase Buck Converter With On-Chip Capacitor Dynamic Re-Allocation and Fine-Grained Phase-Shedding Techniques

This article presents a fully integrated multi-phase (MP) buck converter for on-chip power management units. A peak-and-valley differential sensing (PVDS) scheme based on a flying capacitor is proposed to evenly balance the multiple inductor currents without significant power overhead even under mismatches in inductances, parasitic series resistances, and control-signal skews among phases. In addition, dynamic re-allocation of on-chip capacitors enables an even more optimal frequency response and output ripple based on the number of activated phases. It also improves the chip area efficiency, resulting in a higher power density. The proposed DLL-based MP clock generation provides high granularity in the phase-shedding control to achieve high efficiency over a wide load range. The proposed fully integrated buck converter using six bond-wire inductors (1 nH) was fabricated in a 28-nm CMOS process. The chip running at a frequency of 400 MHz/phase can finely adjust the number of active phases by an integer step ranging from 1 to 6 through sensing a load current. A maximum power density of 1.23 W/mm2 and a peak efficiency of 83.7% were measured. This work achieved an ultra-fast dynamic voltage scaling (DVS) rate of 75 mV/ns.

Design of DC Magnet Power Supply System for ITER Static Magnetic Field Test Facility

International Thermonuclear Experimental Reactor (ITER) static magnetic field (SMF) test facility requires a dc power supply with low voltage, high current, and low harmonics under high power density. Due to the limitation of switching loss, there is a contradiction between the output current capability and the output ripple. Large output current usually leads to low switching frequency, and low switching frequency will generate a large number of harmonics. To solve the problems, a topology based on the interleaving parallel buck converter is used and tested in this article. Moreover, the topology is realized with only a small number of switching metal–oxide–semiconductor field-effect transistors (MOSFETs). This article introduces the system design scheme and control method in detail. The analysis of harmonic and simulation is carried out. The validity of the proposed scheme and control strategy was confirmed by experiments, and the power supply system can supply a large current of 12.23 kA and has the ability of low ripple.

Digital Control and Power Systems for the Pegasus-III Experiment

The PEGASUS-III experiment is a solenoid-free, low aspect ratio spherical tokamak that will serve as a dedicated U.S. platform for comparative nonsolenoidal tokamak plasma startup studies. Approximately 175 megavolt-ampere (MVA) of reconfigured and expanded programmable power systems, 7 MJ of new stored energy, and new digital control and protection systems for the facility are being commissioned to support PEGASUS-III upgrades. These include: increased toroidal field (0.15–0.6 T); new divertor and poloidal field coils; increased pulse length; local and coaxial helicity injectors for solenoid-free plasma initiation; radio frequency (RF) systems for heating and current drive; and a diagnostic neutral beam (DNB). A new real-time digital control system implements 16 proportional-integral differential (PID) feedback controllers with 25 kHz loop rates to control the electromagnets and helicity injectors. The poloidal field coils, helicity injector arc currents, and toroidal field are driven by 36 3.6 MVA (4 kA, 900 V) insulated-gate bipolar transistor (IGBT) buck converters. Helicity injector bias voltage and current will be provided by a set of four 10.8 MVA multi-level buck converters (MLBCs). Each is comprised of an 1800 V integrated gate-commutated thyristor (IGCT) stage and a ±900 V IGBT stage in series, providing controllable <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm {inj}}\le 4$ </tex-math></inline-formula> kA at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {inj}}\le 2.7$ </tex-math></inline-formula> kV. A field programmable gate array (FPGA)-based digital fault protection system multiplexes controller commands to individual power semiconductors in these supplies, monitors their operational status, and executes shutdown sequences within <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10~\mu \text{s}$ </tex-math></inline-formula> of fault detection. An 80 kV, 4 A zero-voltage-switching (ZVS) resonant converter with < 1% output ripple is under development for the DNB and is being evaluated as a topology to drive RF sources.

Temperature Characteristic Analysis of the Output Intrinsically Safe Buck Converter and Its Design Consideration

Aiming at the unreliability resulting from ignoring the temperature effect and randomness of switching frequency in the traditional design method of an intrinsically safe Buck converter, a reliable design method based on the minimum frequency and considering the temperature characteristic is proposed. The theoretical design range of capacitance is deduced according to the maximum output ripple voltage and output intrinsic safety performance requirements. Considering the temperature characteristics of the capacitor, the actual maximum and minimum capacitances are obtained corresponding to the theoretical design capacitance within a given temperature range. It is pointed out that the actual minimum capacitance increases with the decrease of switching frequency, while the actual maximum capacitance is independent of frequency. Therefore, it can be deduced that there exists a minimum frequency which can meet the requirements of both output ripple voltage and intrinsically safe performance. When the actual maximum capacitance equals the actual minimum capacitance, the analytic expression of the minimum frequency is obtained. Assuming a capacitance adjustment, the actual working frequency of the converter corresponding to the minimum frequency is deduced. The design flow of an intrinsically safe Buck converter based on the minimum switching frequency considering the temperature characteristic is presented. The correctness of the theoretical analysis and the feasibility of the proposed design method are verified by experimental results. This design method can also be applied to other types of intrinsically safe converters.

Frequency-Based Active Ripple Compensation Technique to Reduce Bulk Capacitance in Integrated Offline LED Drivers

In order to increase the power density and the lifespan of LED drivers, several studies have proposed Active Ripple Compensation (ARC) techniques for minimizing the converter bulk capacitance. However, a common side-effect of the ARC method is the increase in the Total Harmonic Distortion (THD) of the converter input current. In this context, a frequency-based ARC technique is proposed as an alternative to the conventional ARC methodology, in which the duty-cycle is modulated. The analyses presented in this paper show that the frequency-based ARC approach applied to resonant converters has a better performance than the one used in hard-switching converters, since it allows for a huge capacitance reduction with a small THD increase. Furthermore, this paper presents a generalized analysis of ARC techniques applied to integrated off-line LED drivers, which reduce the number of components and the overall LED driver cost. The input current harmonic content and the output ripple reduction have been theoretically predicted for several converters. Experimental results gathered from a 96-W laboratory prototype supplied from a 127-V 60-Hz grid attested the superior performance of the frequency-based active ripple compensation, since a capacitance reduction of 66.6% has been obtained with an increase of only 0.9% in the THD.

Supercapacitor-Assisted Low-Dropout Regulator Technique for Low Output Ripple DC–DC Conversion

Supercapacitor-assisted low dropout (SCALDO) regulator is an emerging technique to design high-efficiency dc–dc converters based on supercapacitor energy recovery method alongside a low dropout regulator. This very low frequency technique, having low electromagnetic compatibility issues, provides high-efficiency operation applicable to a wide range of output currents varying from a few 100 mA cases with integrated circuit type LDOs to over 100 A cases in the high current discrete form of LDOs. The SCALDO regulator is not a variation of switched capacitor converters due to several definitive reasons. Based on a 12-5 V implementation, this article demonstrates how a SCALDO regulator keeps a very low voltage ripple at the connected dc load while achieving high end-to-end efficiency.

An Advanced MPPT Scheme for PV Systems Application with Less Output Ripple Magnitude of the Boost Converter

The purpose of this paper is to enhance the performance and tracking efficiency of solar photovoltaic systems. This aim can be achieved by operating the photovoltaic array at its optimum power and reducing the output ripple problem of DC-DC converters that affect and stress sensible electronic loads. In view of that, an advanced maximum power point (MPP) tracking (MPPT) scheme, which can guarantee zero oscillation tracking of the accessible MPP and less ripple magnitude on the output side of the DC-DC boost converter, is used. Various simulations are carried out under three conditions of solar irradiance variation, namely, standard test conditions (STC), rapid, and Sin scenarios, using the MATLAB/Simulink® environment, to assess and benchmark the robustness of the tracking of the new MPPT scheme over the celebrated Increment of Conductance (INC) MPPT scheme. Based on the simulation results, the proposed scheme can significantly improve tracking accuracy and reduce the magnitude of ripples on both sides of the boost converter compared to the INC scheme. Certainly, the proposed scheme can provide a shorter time response (0.011 seconds) to locate and track the expected MPP, which is 2.55 times less than that of the INC scheme; a zero power magnitude oscillation instead of 15.9 watts of the INC scheme; and six-time minimization of the magnitude of output voltage ripples compared to the INC scheme. Furthermore, the suggested MPPT scheme has the better tracking efficiency in all scenarios; 99.86%, 99.60%, and 99.62% in the STC, rapid, and Sin scenarios, respectively, with an average value of 99.69% compared to the INC MPPT scheme, which has 94.23%, 95.28%, and 97.87% in the STC, rapid, and Sin scenarios, respectively, with a moderate average tracking efficiency of 95.79%. Finally, the accuracy and tracking performance of the proposed MPPT scheme are verified by real-time examination using the RT-LAB simulator. According to the results obtained, the proposed scheme provides the highest tracking efficiency of 99.80% and 97.77% under the STC and sudden insolation change scenarios, respectively, compared to the INC scheme, which shows, respectively, 97.8% and 96.5% under both scenarios.

Application of DC-DC Converter in Sensor and MEMS Device Integration and Packaging

DC-DC (direct current controlled direct current) converter is the core control circuit in the field of power electronics technology. Based on the theory of sensors and MEMS (microelectromechanical systems), this paper constructs a DC-DC converter device integration and packaging model and proposes an enhanced current equalization technology with offset correction function suitable for two-phase DC-DC converters. Aiming at the generation mechanism of the output ripple of the two-phase DC-DC converter, the model adopts the ripple elimination technology based on the interleaved synchronous clock and the self-calibration interleaved time generator, so that each phase of the converter is accurately staggered within the full-load range, and the problem of output ripple amplitude is solved. During the simulation process, a high-performance two-phase DC-DC converter chip is designed and implemented, which includes an adaptive on-time control logic based on ripple feedback, a self-calibrating zero-current turn-off circuit, and a robust power switch transistor drive logic. The experimental results show that the full-load current of the chip reaches 6A, the peak efficiency is 91%, the phase-to-phase current error is &lt;0.6%, and the output ripple is &lt;9 mV. In the 90.265 V AC input, 0-10 W load range, the output voltage error is less than 0.96%, when the load is switched between no-load and full-load, and the system response speed is less than 200 ps, which effectively improves the overall performance of the DC-DC converter.

Design of a photovoltaic mppt charge controller using DC-DC zeta converter with a modified three-stage charging method

Nowadays, one of the primary kinds of renewable energies is photovoltaic (PV) systems. In standalone PV systems, the battery charge controller plays an important role in the system efficiency. In the maximum power point tracking (MPPT) charge controller, due to adjusting the voltage level and tracking the maximum power, DC-DC converter and MPPT algorithm are used. ZETA converter, as a DC-DC converter, offers a low output ripple. In the proposed MPPT charge controller, a DC-DC ZETA converter accompanied by a P&amp;amp;O (perturb and observe) algorithm will be used for tracking maximum power. Furthermore, over-charging and gassing are phenomena that may reduce the battery life by increasing the battery's temperature. To overcome this obstacle, the proposed three-stage charging method, which is the battery charging voltage levels (bulk, absorption, and float) are based on the battery temperature. The proposed MPPT charge controller is used for providing lower temperature for the battery when being charged. By comparing the proposed MPPT charge controller with the conventional method, the simulation results can ensure the desired performance of the proposed charge controller.

An enhanced ultra-wideband single phase hybrid supply envelope tracking modulator for modern wireless communications

This paper presents a Single Phase Hybrid Supply Envelope tracking Modulator (HSEM) for RF-Power Amplifiers (RF-PAs) used in modern wireless communication systems such as 5G and 6G applications. The proposed HSEM consists of an ultra-wideband linear amplifier to track the input signals with several Mega Hertz of bandwidth, a switching amplifier to provide a high-efficiency supply voltage for the main power amplifier, and a new sensing circuit to generate the required voltage for the switching amplifier. The designed HSEM uses a two-stage rail-to-rail linear class-AB amplifier with constant Gm, high gain bandwidth (GBW), high slew rate (SR), and good phase margin (PM). Most conventional modulators use a sensing resistor or a resistor structure that increases the output ripple and the power loss. The proposed structure uses a linear amplifier output stage sensing circuit and a hysteresis low power current comparator without any resistors, external capacitors, filters, or multi-phase modulator structures. Additionally, using a current comparator eliminates the need for an external reference voltage or a current-to-voltage converter. The proposed structure does not need to remove the switching ripple through the linear amplifier, leading to a more relaxed linear amplifier design. A comprehensive analysis and guide on how to optimally select the inductor values, and the mathematical equation for the switching frequency of the hybrid modulator is given. The efficiency of the proposed structure is 84.3 %, and the maximum output power is 27.3dBm. The average output ripple is 4.16 mV in the wide range of the input voltages, and its minimum is 0.4 mV. In addition, the new structure can track a signal with 400 MHz bandwidth with FOM of the HSEM about 18. The proposed modulator is suitable for broadband and emerging telecommunications applications such as 5G and 6G, and as a power supply for RF power amplifiers. The proposed HSEM is evaluated with TSMC 180 nm CMOS technology parameters.

Intelligent Optimization of Switched Reluctance Motor Using Genetic Aggregation Response Surface and Multi-Objective Genetic Algorithm for Improved Performance

In this paper, a thorough framework for multiobjective design optimization of switched reluctance motor (SRM) is proposed. Selection of stator and rotor pole embrace coefficients is an essential step in the SRM design process since it influences torque output and torque ripple in SRM. The problem of determining optimal pole embrace is formulated as a multi-objective optimization problem with the objective of optimizing average torque, efficiency and torque ripple, and response surface models were obtained based on the genetic aggregation method. The results obtained by genetic aggregation response surface (GARS) and the non-dominated genetic algorithm (NSGA-II) were validated with the finite element method (FEM) model of the initial SRM. The optimized model displayed better efficiency profile over a wide speed range. The initial and optimized models recorded maximum efficiencies of 85% and 94.05%, respectively, at 2000 rpm. The efficiency values of 93.97–94.05% were achieved for the three pareto optimal candidates. The findings indicate the viability of the suggested strategy and support the use of GARS and NSGA-II as useful methods for addressing SRM key challenges.

A new family of bidirectional DC-DC power converters with very low input and output ripples

Bidirectional DC-DC converters with very low ripple contents in the input and output sides are desirable in many applications. This paper proposes a new family of bidirectional DC-DC converters with very low input and output ripples that is derived from the conventional Cuk DC-DC converter. At first, a new family of single-phase DC-DC converter is derived. Then, extension of this family into the multiphase ones is presented. Output voltage expressions of the proposed DC-DC converters are presented. It is found that the derived DC-DC converters have lower conduction losses than the conventional DC-DC converters. Expressions of input and output ripples of the proposed DC-DC converters are then also presented. Finally, some experimental results are included to show the basic performance of the proposed converters. Thus, the outcome of the proposed DC-DC converter can be achieved by using the duty ratio is half and the multiphase technique is upper-middle inductors. It given that the current and voltage ripples of proposed DC-DC converter is very low and almost zero.

High gain transformer-less inverter based-on capacitor clamping multi-phase boost converter

The boosting converters integrated with inverters are widespread use in many applications under transformerless inverter titles, including powered vehicles, PV systems, fuel cells systems and so on. Reliability, quality, maintainability, and reduction in size are important requirements in the energy conversion process. The multi-phase boost converter can be adopted as a good solution with high power applications. The multi-phase boost enhanced by clamping capacitor structure is providing low ripple, high gain and evident improvement in the efficiency when compared to the conventional converters. This paper investigates the transformerless inverter based on a capacitor clamping multi-phase boost converter. High gain proposed architectures are being designed to step-up voltage. The converter features a high voltage gain offers additional solutions based on the capacitor clamping structure. The proposed architectures are being designed to optimize the gaining in popularity as they are increasing the voltage gain and the efficiency and mitigate the switching frequency effect. The investigation of validation performance was introduced through the steady-state analysis and operation. The operation modes and mathematical analysis are presented. To validate the performance in terms of input and output ripple and values, the converters were tested using MATLAB / SIMULINK. The results supported the mathematical analysis. The voltage gains increased, reduce of ripple in input current and the output voltage is significantly detected. The switches stresses at the converter side are One-third of the output voltage.

SiC-MOSFET three phase unbalance compensation device with interleaved parallel structure

In this paper, a three-phase unbalance compensation device with two-module interleaved parallel structure is proposed, which can reduce the harmonic of output voltage and output ripple current. Meanwhile, by using SiC-MOSFET as the switching device, the switching frequency of the device has been increased to 50 kHz to increase the harmonic frequency of the output voltage. With the above two designs, only a single L filter can be used to effectively filter the output voltage harmonics of the inverters, and the detection and compensation accuracy is also optimized. A 50 kVA prototype has been fabricated based on the theories above, which is at least half smaller than a conventional device of the same capacity. The PI + repeat controller (RC) is used to achieve the none-static-error tracking of sinusoidal signals, so as to achieve a good compensation effect.