Output Jitter Research Articles

An All-Digital Approach to Supply Noise Cancellation in Digital Phase-Locked Loop

With increased levels of integration in modern system-on-chips, the coupling of supply noise in a phase-locked loop (PLL) has become the dominant source of performance degradation in many systems. In this paper, an all-digital approach to canceling the effects of supply noise is presented. By sensing the supply noise using an analog-to-digital converter (ADC), an observer–controller loop filter jointly processes the ADC and phase detector outputs to determine the oscillator control signals that minimize the output jitter. The proposed digital PLL is shown to be significantly more robust to supply noise compared with a conventional PLL.

A 3.3 GHz Spread-Spectrum Clock Generator Supporting Discontinuous Frequency Modulations in 28 nm CMOS

Spread-spectrum clocking is an established approach to mitigate electromagnetic interference (EMI) of digital circuits, by intentionally sweeping the clock frequency. In this way, the energy of each clock harmonic is spread over a larger bandwidth, thereby reducing the peak of the interfering spectrum. This paper describes an highly flexible all-digital spread-spectrum clock generator (SSCG) realized with a standard-cells design flow. The developed circuit supports discontinuous frequency modulation profiles (with improved EMI reduction capability) and features reduced output jitter, due to delay interpolators and digital compensation of delay path asymmetries. The proposed SSCG is ideally suited for complex system on chips applications, having programmable spreading parameters, frequency synthesis capability and reduced recovery time to support local standby modes. The SSCG is implemented in bulk 28 nm CMOS technology, presents a maximum working frequency of 3.3 GHz and less than 3.2 ps $_{\rm rms}$ output jitter. The measured peak level reduction of the clock power spectrum, at 1.0 GHz output frequency, is 27.0 dB with a 10% modulation depth. The power dissipation is 29.3 mW @ 3.3 GHz and the area occupation is 0.031 mm.

An All-Digital Delay-Locked Loop Using an In-Time Phase Maintenance Scheme for Low-Jitter Gigahertz Operations

Traditional all-digital delay-locked loops (ADDLLs) have a long control loop, and false skew compensation may occur due to late code adjustment. To avoid this problem, the ADDLLs either simply sacrifice the maximum operating frequency or adopt a lower code adjustment rate to achieve a higher maximum operating frequency. However, lowering the code adjustment rate not only increases the number of the locking cycles but also results in large output jitter because the clock skew induced by run-time variations cannot be compensated in time. This paper presents a 55 nm 1.0 V 0.1-to-2.5 GHz ADDLL, which is constructed on a previously proposed half-delay-line skew-compensation circuit with several new circuit design techniques developed to achieve low jitter, small area, low power, fast lock-in, and high PVT- variation tolerance across a large operating frequency range. The key design feature is a ping-pong phase maintenance scheme that allows the code adjustment to be performed in time in each clock cycle, even for gigahertz operations. The measurement results show that the ADDLL achieves a peak-to-peak (p-p) jitter of 3 ps with 1.96 mW power consumption and 8 lock-in cycles when operated at 2.5 GHz.

Modeling and Jitter Improvement of SRD-Based Ultra-Wideband Pulse Generator

Step recovery diode (SRD)-based ultra-wide band (UWB) pulse generators (PGs) suffer from jitter caused by AM-to-PM conversion, SRD shot noise, and clock jitter. These noise sources significantly impact the accuracy of UWB systems if very high precision ranging/positioning is required. Jitter behavior caused by the transmitter and receiver is mostly detrimental in the equivalent time-sampling receiver. Thus, a mathematical model for simulation of the jitter and amplitude variation effect in the equivalent time-sampling technique has been developed and used in SystemVue simulations. A criterion as an estimate of system accuracy is defined as signal-to-distortion ratio (SDR) and used. Similarly, a model for AM and PM noise analysis for an SRD-based UWB PG is developed that was validated experimentally. In addition, SRD shot-noise contribution on output jitter was evaluated using the proposed model. Based on these models, methods to reduce the output jitter of the system have been recommended. Simulation showed that clock jitter and SRD shot noise led to pronounced output jitter, with shot noise the primary cause. For a typical SRD-based UWB PG, an output jitter of around 3 ps has been achieved using improvement techniques based on the proposed method, compared to a 15-ps jitter before improvement. These measured results are in good agreement with our predictions.

1.9-ps Jitter, 10.0-dBm-EMI Reduction Spread-Spectrum Clock Generator With Autocalibration VCO Technique for Serial-ATA Application

A spread-spectrum clock generator (SSCG) that is characterized by a low jitter voltage-controlled oscillator (VCO) with a high-frequency limiter and an autocalibration function is developed for a Serial-ATA application. The high-frequency limiter prevents the SSCG from going into an unlocked state. The proposed VCO achieved far less jitter than a conventional one because a proposed structure has fewer operating MOSs that are noise sources. The autocalibration technique calibrates the VCO sensitivity, the maximum frequency of the VCO output signal, and the characteristics of the limit function to prevent the SSCG from degrading an output jitter and an electromagnetic interference (EMI) reduction due to a process variation. The proposed SSCG with the autocalibration function was fabricated in a 0.13-μm CMOS process. The variation in the jitter in 250-cycles at 1.5 GHz with spread-spectrum clocking (SSC) is improved from 2.1-7.8 ps to 1.9-3.3 ps and the EMI reduction is achieved as 10.0 dBm by the proposed autocalibration technique.

A Jitter Compensating PID Controller to Mitigate the Detrimental Effects of Software Induced Jitter in Digital Control Systems

Software induced delays in a digital control system can lead to degradation in performance and as a result plant response characterizing performance requirements such as percent overshoot, rise time, and settling time can be violated. In the worst case the digital control system can become unstable. These delays can be constant or varying from one period to the other. The latter type of delay is known as jitter. Existing solutions attempt to improve the performance of digital control systems in the presence of software induced delays notwithstanding shortcomings. These include but are not limited to, a lack of regard for satisfying plant response characterizing performance requirements, implementation complexity, and an increase in the runtime overhead to execute the solution. In addition, a solution to compensate for inputoutput and output jitter for proportional integral derivative (PID) controllers is not available in the literature. Taking the problem to be solved and shortcomings in the literature into account, this paper proposes method to design a discrete-time PID controller that compensates for sampling, input-output, and output jitter. The solution initially models the worst case delay between input to output and then places it in a model of the digital control system in the forward loop between the PID controller and plant. Subsequently, the PID controller is tuned to satisfy plant response characterizing performance requirements. The two main advantages of this solution is that plant response characterizing performance requirements are satisfied and the execution time of the PID controller remains unchanged. An evaluation of the performance using a step input experiment validate that the proposed solution is capable of satisfying plant response characterizing performance requirements whereas the uncompensated counterpart failed to satisfy one requirement. A square wave tracking experiment also demonstrated that the proposed solution improved performance.

Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops

Digital phase-locked loops based on bang-bang phase detectors are attractive candidates for low-jitter clock-frequency multiplication. Unfortunately, the coarse quantization of phase error makes these systems prone to the generation of limit cycles appearing as unwanted spurs in the spectrum. The random noise contributed by building blocks and acting as dithering signal can eliminate those spurs. The quantitative analysis of those phenomena becomes more involved when a DCO with relaxed intrinsic resolution, such as a ΔΣ-DCO is employed, and when practical spectra of random noise sources are considered. In this work, the expression of jitter is calculated in closed-form taking into account the quantization, introduced by both phase detector and DCO, and the phase noise of DCO, with both 1/f 2 and 1/f 3 components. Combining these results, a closed-form expression of the total output jitter as a function of loop parameters and noise sources is developed which suggests a minimum-jitter design strategy. The proposed analysis and optimization are validated both numerically and experimentally on a 320-MHz digital bang-bang PLL fabricated in a 65-nm CMOS process.

Holistic schedulability analysis for multipacket messages in AFDX networks

The ARINC-664, Part 7 (AFDX) standard defines a communication network based on Ethernet and the UDP/IP protocols. Contrary to general-purpose Ethernet, the timing behavior in AFDX is deterministic due to the use of special network switches and end systems with static routing tables and traffic policing at the sending end through mechanisms called virtual links. Even though the latencies in this network are bounded, there are scheduling and contention effects that need to be analyzed. In this paper we develop a response-time analysis for multipacket messages transmitted through an AFDX network including the scheduling of the virtual links and sub-virtual links, and also the contention in the end systems and in the switches. This analysis allows us to obtain worst-case latencies and output jitter for the network messages with a precise modeling of the sending and receiving ends. These results can be integrated in a holistic approach with the response time analysis of the threads in the processing nodes to obtain end-to-end response times in heterogeneous distributed systems.

A clock generator for a high-speed high-resolution pipelined A/D converter

A clock generator circuit for a high-speed high-resolution pipelined A/D converter is presented. The circuit is realized by a delay locked loop (DLL), and a new differential structure is used to improve the precision of the charge pump. Meanwhile, a dynamic logic phase detector and a three transistor NAND logic circuit are proposed to reduce the output jitter by improving the steepness of the clock transition. The proposed circuit, designed by SMIC 0.18 μm 3.3 V CMOS technology, is used as a clock generator for a 14 bit 100 MS/s pipelined ADC. The simulation results have shown that the duty cycle ranged from 10% to 90% and can be adjusted. The average duty cycle error is less than 1%. The lock-time is only 13 clock cycles. The active area is 0.05 mm2 and power consumption is less than 15 mW.

Glitch-Free NAND-Based Digitally Controlled Delay-Lines

The recently proposed NAND-based digitally controlled delay-lines (DCDL) present a glitching problem which may limit their employ in many applications. This paper presents a glitch-free NAND-based DCDL which overcame this limitation by opening the employ of NAND-based DCDLs in a wide range of applications. The proposed NAND-based DCDL maintains the same resolution and minimum delay of previously proposed NAND-based DCDL. The theoretical demonstration of the glitch-free operation of proposed DCDL is also derived in the paper. Following this analysis, three driving circuits for the delay control-bits are also proposed. Proposed DCDLs have been designed in a 90-nm CMOS technology and compared, in this technology, to the state-of-the-art. Simulation results show that novel circuits result in the lowest resolution, with a little worsening of the minimum delay with respect to the previously proposed DCDL with the lowest delay. Simulations also confirm the correctness of developed glitching model and sizing strategy. As example application, proposed DCDL is used to realize an All-digital spread-spectrum clock generator (SSCG). The employ of proposed DCDL in this circuit allows to reduce the peak-to-peak absolute output jitter of more than the 40% with respect to a SSCG using three-state inverter based DCDLs.

A Dividerless PLL With Low Power and Low Reference Spur by Aperture-Phase Detector and Phase-to-Analog Converter

A 2.1-GHz dividerless PLL with low power, low reference spur and low in-band phase noise is introduced in this paper. A new phase detection mechanism using aperture-phase detector (APD) and phase-to-analog converter (PAC) generates an analog voltage in proportion to the phase error between reference and VCO, and then controls the current amplitude of the following charge pump (CP). The charging and discharging currents in the proposed CP have equal pulse width and equal small amplitude in locked state, which reduces the reference spur and power consumption of the CP effectively. Moreover, compared to the conventional CP with the same bias current in locked state, the proposed CP can contribute a much lower noise to the PLL output. In addition, a method of tunable loop gain with theoretical analysis is introduced to reduce the PLL output jitter. The proposed PLL is fabricated in a standard 0.13- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu$</tex></formula> m CMOS process. It consumes 2.5 mA from a 1.2-V supply voltage and occupies a core area of 0.48 mm <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,\times\,$</tex> </formula> 0.86 mm. The reference spur of the proposed PLL is measured to be <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}80$</tex></formula> dBc/ <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}74$</tex></formula> dBc and an in-band phase noise of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}103$</tex> </formula> dBc/Hz at 100 kHz offset is achieved.

A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme

A 1.2 V 4 Gb DDR4 SDRAM is presented in a 30 nm CMOS technology. DDR4 SDRAM is developed to raise memory bandwidth with lower power consumption compared with DDR3 SDRAM. Various functions and circuit techniques are newly adopted to reduce power consumption and secure stable transaction. First, dual error detection scheme is proposed to guarantee the reliability of signals. It is composed of cyclic redundancy check (CRC) for DQ channel and command-address (CA) parity for command and address channel. For stable reception of high speed signals, a gain enhanced buffer and PVT tolerant data fetch scheme are adopted for CA and DQ respectively. To reduce the output jitter, the type of delay line is selected depending on data rate at initial stage. As a result, test measurement shows 3.3 Gb/s DDR operation at 1.14 V.

The Impact of Input-Mismatch on Flying-Adder Direct Period Synthesizer Output Jitter

Flying-Adder direct period synthesis is an emerging frequency synthesis technique. It is a mixed-signal technology that directly constructs the output clock period based on a multi-inputs reference. Owing to its open loop style and the usage of Time-Average-Frequency, this technique bears two important features: fine frequency resolution and instantaneous response. Although it has been used in commercial products for over a decade, the important issue associated with design/layout mismatch among its multi-inputs has not been studied in depth. In this paper, through a 55 nm Flying-Adder implementation, the cause of the mismatch is investigated. A mismatch model is created. Based on the model, the mismatch's impact is studied both in time and frequency domain. The experimental data from the chip is used to verify the observations from the analysis. Some useful insights are summarized in the end which will be useful in guiding future designs for commercial products. This study could also be helpful in developing a general theory for this problem.

An Experimental Method to Extract the Phase-Sensitivity of Oscillators to Noise Perturbations

This paper describes an original experimental procedure to extract the phase-sensitivity of oscillators to noise perturbations. The proposed method relies on measuring the width of the locking ranges over which the oscillator's response synchronizes with injected small-amplitude signals. It is shown that this sensitivity function can be employed to accurately predict how inner noise sources are transferred to output phase-noise and jitter. The extraction procedure is applied to a relaxation oscillator that exhibits a strongly nonlinear behavior.

Optimum Digital Filter for High-Performance All-Digital Phase-Locked Loop

The effect of all-digital phase-locked loop (ADPLL) digital filter parameters on the jitter is investigated in time domain, and a systematic design procedure for ADPLL is presented. The pro-posed method not only estimates the output jitter of an ADPLL, but also finds the optimal filter pa-rameter minimizing the overall ADPLL timing jitter. To verify the theoretic analysis, an ADPLL behavior model in matlab is designed. The simulation shows significant performance improvement on the timing jitter.

Carrier, Symbol and Block Synchronizers

The general PLL (Phase Lock Loop) is a device (LOOP) whose VCO (Voltage Controlled Oscillator) is able to follow (LOCK) the input signal phase (PHASE). However, the input signal can be a carrier regular sinusoidal wave, or a symbol/bit/data random stream, or a block of bits. So, in this direction, we have respectively the Carrier Synchronizer (CPLL), the Symbol Synchronizer (SPLL) and the Block Synchronizer (BPLL). The carrier synchronizer can be adapted as synthetizer of frequencies with different carriers. The symbol synchronizer recovers the clock of a synchronous system and can operate at different rhythms. The block synchronizer can produce streams of different bit rates. The three synchronizer prototypes can be adapted to different systems. Other objective is to study the output jitter UIRMS (Unit Interval Root Mean Square) versus input SNR (Signal noise ratio).

Optimization analysis on the bandwidth algorithm for the phase-locked loop (PLL) in OTU

The bandwidth of phase-locked loop (PLL) in optical transponder unit (OTU) is affected by both the external input jitter and the internal phase noise jitter, so the selection for the bandwidth of the PLL has a contradiction and it is necessary that the bandwidth is optimally designed. Under the consideration of both the external input jitter and the internal phase noise, the bandwidth algorithm of the PLL is comprehensively analyzed, and the optimization algorithm of the bandwidth for the PLL of the OTU can be deduced and obtained through improving the former calculation and analytical methods. The optimal bandwidth of the PLL has been analyzed and obtained so as to ensure that the clock output of the OTU has a lower jitter noise. And then the optimization algorithm is applied in 2.5Gbit/s and 10Gbit/s OTU, the optimal parameters of the PLL and the output jitter value of the OTU have been acquired by taking the quantitative and qualitative analysis of the PLL parameters. The study shows the optimization algorithm is superior and feasible as well as it is better used in the OTU and plays an important part in the practical application.

A dividing ratio changeable digital PLL with low jitter using a multiphase clock divider

AbstractSince phase‐locked loops (PLL) are used in the clock extraction of digital communications and high‐density digital recording, it is required to have simultaneously low jitter, fast pull‐in, and wide lock‐in range characteristics. However, in the case of the conventional dividing ratio changeable digital PLL based on phase state memory and double clock‐edge detection (PM‐DCPLL), the output jitter in the steady state becomes no less than half the pulse width of the base clock controlling the loop, and the upper bound frequency of the lock‐in range is limited accordingly. In this paper, we propose a dividing ratio changeable digital phase‐locked loop (MC‐DCPLL) with low jitter, wide lock‐in range, and fast pull‐in characteristics using a multiphase clock divider. Since the output jitter of this circuit is one phase difference of the multiphase clock in steady state, the circuit can reduce the output jitter to 1/k of that of a conventional PM‐DCPLL when a k phase clock is used. Therefore, the upper bound frequency becomes k times that of a conventional PM‐DCPLL. Furthermore, the initial pull‐in is completed in one period of the input signal by using the initial pull‐in circuit. © 2011 Wiley Periodicals, Inc. Electron Comm Jpn, 94(11): 55–62, 2011; Published online in Wiley Online Library (wileyonlinelibrary.com). DOI 10.1002/ecj.10340

Output-Jitter Performance of Second-Order Digital Bang-Bang Phase-Locked Loops With Nonaccumulative Reference Clock Jitter

Bang-bang phase-locked loops (BBPLLs) are inherently nonlinear systems due to the binary phase detector (BPD). While they are typically used for clock and data recovery, the ongoing trend toward digital loop implementations has resulted in several digital BBPLLs (DBBPLLs) suitable for frequency synthesis. This brief investigates the effect of nonaccumulative reference clock jitter (due to white phase noise) in second-order DBBPLLs, comparing the output jitter with that of first-order DBBPLLs. For small clock jitter, the nonlinear loop behavior is modeled as a 2-D Markov chain, and the output jitter is smaller than but close to that of a first-order loop. For large clock jitter, the BPD nonlinearity is linearized, and the output jitter is larger than that of a first-order loop; it is proportional to the clock jitter and inversely proportional to the square root of the stability factor-the ratio of the proportional-path gain to the integral-path gain of the digital loop filter.

Discrete-Time, Linear Periodically Time-Variant Phase-Locked Loop Model for Jitter Analysis

Timing jitter is one of the most significant phase-locked loop (PLL) characteristics, which directly affects the performance of the system in which the PLL is used. It is, therefore, important to develop the tools necessary to study and predict PLL jitter performance at design time. In this paper a discrete-time, linear, periodically time-variant integer-N PLL model for jitter analysis is proposed, which accounts for the periodically time-varying effect of noise injected into the loop at various PLL components, such as VCO, charge pump, VCO buffer, VCO control node, and divider. The model also predicts the aliasing of jitter due to the downsampling and upsampling of the jitter signal around the PLL loop. Closed-form expressions are derived for the output jitter spectrum and match well with results of event-driven simulations of a third-order PLL.