Abstract

Software induced delays in a digital control system can lead to degradation in performance and as a result plant response characterizing performance requirements such as percent overshoot, rise time, and settling time can be violated. In the worst case the digital control system can become unstable. These delays can be constant or varying from one period to the other. The latter type of delay is known as jitter. Existing solutions attempt to improve the performance of digital control systems in the presence of software induced delays notwithstanding shortcomings. These include but are not limited to, a lack of regard for satisfying plant response characterizing performance requirements, implementation complexity, and an increase in the runtime overhead to execute the solution. In addition, a solution to compensate for inputoutput and output jitter for proportional integral derivative (PID) controllers is not available in the literature. Taking the problem to be solved and shortcomings in the literature into account, this paper proposes method to design a discrete-time PID controller that compensates for sampling, input-output, and output jitter. The solution initially models the worst case delay between input to output and then places it in a model of the digital control system in the forward loop between the PID controller and plant. Subsequently, the PID controller is tuned to satisfy plant response characterizing performance requirements. The two main advantages of this solution is that plant response characterizing performance requirements are satisfied and the execution time of the PID controller remains unchanged. An evaluation of the performance using a step input experiment validate that the proposed solution is capable of satisfying plant response characterizing performance requirements whereas the uncompensated counterpart failed to satisfy one requirement. A square wave tracking experiment also demonstrated that the proposed solution improved performance.

Highlights

  • Software that implements the functionality of a digital control system usually executes in a periodic manner

  • Execution of the analog to digital (A/D) conversion via the analog to digital converter (ADC), digital to analog (D/A) conversion via the digital to analog converter (DAC), control law, and other software routines such as interrupt service routines (ISRs), and real-time operating system (RTOS) scheduler and context switching introduce a delay between sampling of inputs and outputting the control law to the plant

  • This paper considers a collection of multiple independent single input single output (SISO) digital control systems executing in parallel on a single processor and this collection is referred to as a digital control system set

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Summary

Introduction

Software that implements the functionality of a digital control system usually executes in a periodic manner. The negative effect of software induced delays (both constant and jitter) is a performance degradation, which in the worst case can lead to a violation of performance requirements It could result in destabilizing the digital control system. Traditional digital control system design methodologies assume that the input sampling, control law calculation, and outputting to the plant all occur simultaneously without any delay This oversight is one of the contributors to the performance degradation issue. The solution that this paper proposes is a discrete-time PID controller capable of compensating for software induced jitter. The solution involves modelling the worst case delay between input sampling and outputting to the plant, and placing this delay in a model of the digital control system in the forward loop between the PID controller and plant. The structure and timing of the digital control system model within a set is refined to represent four realistic ways of implementing a digital control system

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