Abstract
The general PLL (Phase Lock Loop) is a device (LOOP) whose VCO (Voltage Controlled Oscillator) is able to follow (LOCK) the input signal phase (PHASE). However, the input signal can be a carrier regular sinusoidal wave, or a symbol/bit/data random stream, or a block of bits. So, in this direction, we have respectively the Carrier Synchronizer (CPLL), the Symbol Synchronizer (SPLL) and the Block Synchronizer (BPLL). The carrier synchronizer can be adapted as synthetizer of frequencies with different carriers. The symbol synchronizer recovers the clock of a synchronous system and can operate at different rhythms. The block synchronizer can produce streams of different bit rates. The three synchronizer prototypes can be adapted to different systems. Other objective is to study the output jitter UIRMS (Unit Interval Root Mean Square) versus input SNR (Signal noise ratio).
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