Output Balun Research Articles

A Large Dynamic Range Reconfigurable Interpolation Digital Transmitter for NB-IoT Applications

In this letter, we present a digital transmitter for dual-band narrowband-Internet-of-Things (NB-IoT) applications achieving a large dynamic range with high-speed cartesian RF-DACs requiring less area and consuming low power consumption. The proposed transmitter incorporates integrated output baluns, a reconfigurable digital interpolater-based oversampling for DAC image suppression, or avoidance of coexistence channel. A true SAW-less design is realized by external low-cost low-pass filtering of the spurious emission satisfying NB-IoT requirements. Implemented in standard 40-nm CMOS technology with a core area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.1\times1.5$ </tex-math></inline-formula> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and packaged with QFN-68, the transmitter achieves a dynamic range from −47.5 to 24.8 dBm with error vector magnitude (EVM) <−25 dB. The peak efficiency is 44.1% at 28.7-dBm output power, with a 2.4-V power supply.

A 300-GHz Low-Noise Amplifier in 130-nm SiGe SG13G3 Technology

This work presents a 300-GHz low-noise amplifier (LNA) in a SiGe:C 130-nm BiCMOS technology, featuring <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{t}/f_{\text {max}}$ </tex-math></inline-formula> of 470/700 GHz. The designed amplifier uses three cascaded stages in a pseudo-differential cascode topology with input and output baluns facilitating single-ended measurements. The first stage is matched trading off noise and gain performance, while a T-type output matching network is used for broadband matching. The interstage matching is performed using center tap transformers. On-wafer measurements show that the designed LNA has a peak small-signal gain of 10.8 dB at 325 GHz, along with a 3-dB bandwidth of 68 GHz and an input 1-dB compression point of −15.6 dBm at 287.5 GHz. The simulated noise figure is better than 12.7 dB over the required band. The circuit occupies 0.26-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> silicon area and consumes 119 mW from a 3.3-V supply.

300-GHz 2nd-Order Subharmonic Upconversion Mixer Using Symmetric MOS Varactors in 65-nm CMOS

A 2nd-order subharmonic upconversion mixer with an intermediate frequency of 150 GHz and radio frequency (RF) of 290 GHz that employs accumulation mode MOS symmetric varactors is demonstrated in 65-nm complementary metal-oxide-semiconductor. A transformer-based hybrid is utilized to improve port isolation. The mixer achieves the maximum conversion gain of -16 dB including the losses (~2 dB total) of input and output baluns added for measurements. The local oscillator power at 70 GHz was 11.5 dBm and the 27-GHz 3-dB bandwidth spans between 284 and 311 GHz. The -11.6-dBm output 1-dB compression point from a single mixer is the highest among that for the 2nd-order subharmonic mixers with RF of ~300 GHz fabricated in any process technologies.

A 27.5‐43.5 GHz 65‐nm CMOS up‐conversion mixer with 0.42 dBm OP1dB for 5G applications

AbstractA 27.5‐ to 43.5‐GHz up‐conversion mixer is presented for fifth‐generation (5G) applications in 65‐nm CMOS process. A two‐path transconductance stage (TPTS) is demonstrated to improve the linearity. Compared with the conventional common‐source stage, this method enhances the output 1‐dB compression point (OP1dB) by 3.45 dB only at a cost of 1‐mW extra power. Moreover, the input and output baluns are using the fourth‐order transformer‐based resonators to realize a wideband impendence matching. With a power consumption of 14 mW, the proposed up‐conversion mixer achieves OP1dB of 0.42 dBm at 38 GHz. Simultaneously, the maximum conversion gain of −5 dB, local oscillator (LO)‐to‐intermediate frequency (IF) isolation of 43 dB and LO‐to‐radio frequency (RF) isolation of 40 dB are obtained.

Dual-Mode CMOS Power Amplifier Based on Load-Impedance Modulation

This letter presents a dual-mode CMOS power amplifier (PA) that has an improved efficiency using load-impedance modulation in the low-power mode (LPM) and a fully differential operation in the high-power mode (HPM). For the LPM, the transistor in the negative path of the differential pair is turned ON, as a switch, to appropriately modulate the load impedance for the transistor in the positive path using the output balun. An external switch is deployed to turn $V_{\text {DD}}$ OFF for the negative path. In order to verify the proposed concept, a dual-mode CMOS PA IC was designed using a bulk CMOS process and an off-chip output balun, and it was evaluated using the 920-MHz narrow-band Internet of Things signal with a bandwidth of 200 kHz and a peak-to-average power ratio of 5.7 dB. For the HPM, the implemented PA exhibited a gain of 24.1 dB, a power-added efficiency (PAE) of 44.3%, and an adjacent channel leakage power ratio (ACLR) of −33.9 dBc at an average output power of 27.7 dBm. For the LPM, a gain of 19.3 dB, a PAE of 37.7%, and an ACLR of −34.9 dBc were obtained at an average output power of 21.7 dBm.

A 24–28 GHz high-stability CMOS power amplifier using common-gate-shorting (CGS) technique with 17.5 dBm $${\hbox {P}}_{sat}$$ P sat and 16.3% PAE for 5G millimeter-wave applications

This paper presents a 24–28 GHz high-stability millimeter-wave power amplifier (PA) implemented in low-cost $$0.13\, \upmu \hbox {m}$$ CMOS process. The PA consists of two cascode stages with passive transformer-based input and output baluns. The common-gate-shorting technique is proposed for high-stability and high-gain millimeter-wave cascode stage. To realize this technique, an interdigited powercell structure is adopted for MOS layout optimization. In order to improve $$\hbox {P}_{out}$$ and PAE, an inter-stage inductor is introduced. The proposed PA achieves a PAE over 16.3% with a saturated output power of 17.5 dBm. The maximum gain is 21.2 dB at 26 GHz.

Design of a 60-GHz High-Output Power Stacked- FET Power Amplifier Using Transformer-Based Voltage-Type Power Combining in 65-nm CMOS

In this paper, a 60-GHz transformer (TF)-based voltage-type-combined single-stage stacked field-effect transistor (FET) power amplifier (PA) is demonstrated using a 65-nm CMOS process. A stacked-FET structure is adopted in the PA design to overcome the low breakdown voltage limit of MOSFETs. The TF-based voltage-type combiner used in the design has 0.9-dB insertion loss with a compact size of 0.023 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The additional output balun is utilized to transform the differential output of the voltage-type combiner to the single-ended output for testing consideration. The thermal problem of the PA was discovered and improved during measurement. With a 3-V supply, the measured PA achieves the saturated output power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {SAT}}$ </tex-math></inline-formula> ) of 21.8 dBm, the maximum power-added efficiency (PAE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ) of 12.4%, and a 8.7-dB small-signal gain <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(\vert S_{21}\boldsymbol \vert)$ </tex-math></inline-formula> at 60 GHz with the loss of the output balun. Without considering the loss of the output balun, which is 0.825 dB, the measured PA achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {SAT}}$ </tex-math></inline-formula> of 22.8 dBm, the PAE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of 15.9%, and a 9.5-dB gain at 60 GHz.

An ultra-wideband CMOS PA with dummy filling for reliability

A V-band power amplifier in a bulk 65nm CMOS technology with a peak gain 14.5dB and 3-dB bandwidth of 28.8GHz (50.8–79.6GHz) is presented. The techniques to boost bandwidth and power efficiency are presented. In addition, the design of dummy filling to satisfy manufacturing density requirements while having negligible effects on performances is discussed in details. The PA features a three stage transformer coupled differential architecture with integrated input and output baluns on-chip. The PA achieves a measured saturated output power of 15.1dBm and output 1dB compression power of 12.9dBm at 65GHz. The peak power-added efficiency is 18.9%. The entire PA occupies area of 0.31mm2, while consuming 150mW from a 1.25V supply.

A 60-GHz 19.8-mW Current-Reuse Active Phase Shifter With Tunable Current-Splitting Technique in 90-nm CMOS

A 60-GHz 4-bit vector-summing phase shifter has been implemented in a 90-nm CMOS process. Based on a tunable current-splitting technique with $\pi $ -type low-pass filter (LPF) and T-type high-pass filter (HPF), a quadrature adjustable amplitude generator is developed to improve the insertion loss and adjust quadrature signals’ amplitudes. Variable gain amplifiers (VGAs) that are widely used in traditional phase shifters are replaced by the generator to reduce power consumption. In addition, a balun-based current-reuse technique is applied to further save dc power. The overall consumed direct current is 11 mA under 1.8-V voltage supply. The measured results show that the phase shifter with an output balun (with loss of 1.6 dB) achieves gain of $-{{0.4}}{\sim }{{2.5}}~{\text {dB}}$ at 60 GHz and root mean square (rms) gain error is ${{0.75}}{\sim }{{1.6}}~{\text {dB}}$ in the frequency regime from 57 to 64 GHz. The peak average gain is 1.1 dB at 59.7 GHz. By employing a calibration method, the measured rms phase error ranges from 2.3° to 7.6° from 57 to 64 GHz. The tested 60-GHz input 1-dB compression point $(P_{1\mathrm {dB}})$ and noise figure (NF) for 16 phase states are −9.8 ± 0.8 dBm and 11 ± 1.3 dB, respectively.

A CMOS power amplifier using split input and output transformers to minimize its chip area

In this study, we propose a layout technique to reduce the chip area of differential RF CMOS power amplifiers in which input and output transformers are utilized as input and output baluns. To minimize the chip area of the CMOS power amplifier, we split a conventional spiral transformer into two identical parts, thereby making full use of the wasted area in the conventional power amplifier. Using the proposed split transformers in the input and output transformers, we successfully reduce the chip area of the CMOS power amplifier based on a differential structure. To verify the feasibility of the proposed split cascode structure, we designed a 2.4-GHz CMOS power amplifier using a 180-nm SOI RF CMOS process. With an IEEE 802.11n WLAN modulated signal, we obtain a maximum output power of 9.73 dBm. From the measured results, we verify the feasibility of the proposed split transformer structure for RF CMOS power amplifier applications. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:1443–1446, 2016

An 85-W Multi-Octave Push–Pull GaN HEMT Power Amplifier for High-Efficiency Communication Applications at Microwave Frequencies

This paper proposes a design methodology for multi-octave planar push–pull power amplifiers (PPPAs) to tackle the challenges associated with the integration of planar balanced to unbalanced transformers (baluns) with packaged transistors characterized by significant parasitics. This methodology relies on carefully selecting the balun’s placement and adding external matching networks to separately control the odd- and even-mode impedances presented to the power amplifier (PA) to ensure high-efficiency operation over a broad range of frequencies. Proper second harmonic impedances are obtained by placing the balun in close proximity to the transistors’ terminals and repurposing the packaged transistors’ leads into a coupled-line with a high coupling coefficient. Furthermore, adequate odd-mode terminations are realized using broadband matching networks at the unbalanced side of the baluns. Following this methodology, an 85-W PPPA was designed using off-the-shelf packaged gallium–nitride high electron-mobility transistors. The fabricated PA demonstrated drain efficiency and output power above 45% and 46.5 dBm, respectively, over the frequency band spanning from 0.45 to 1.95 GHz. Furthermore, the fabricated PA was successfully linearized using digital predistortion when driven with single- and multi-band modulated signals. Overall, the fabricated PA had the best reported power, efficiency, bandwidth, and second harmonic rejection combination for a multi-octave PPPA designed with input and output baluns using packaged off-the-shelf transistors.

Study of stability problems due to undesired coupling of a RF power amplifier using a distributed active transformer

In this study, we investigate the stability problems induced by undesired coupling between input feed lines and an output transformer for a linear CMOS power amplifier using a distributed active transformer (DAT) as an output balun. We extracted the losses of the input and output transformer, the undesired coupling, and the gains of the driver and the power stages to calculate the closed-loop gain. To determine the possibility of oscillation according to the location of the driver stage related to the undesired coupling and the closed-loop gain, we investigated the stability factor and stability circle. We show that the location of the driver stage of the power amplifier can be used to manage the value of the closed-loop gain. From the analyzed results, the driver stage of the linear power amplifier should be located outside the DAT to mitigate the stability issues.

Split driver stages for a switching mode power amplifier with multipairs of power stages

ABSTRACTIn this study, we analyze the effects of a power splitter on the output power and the power consumption of a CMOS power amplifier using a distributed active transformer as an output balun. On the basis of the analyzed results, we propose a split driver stage structure to mitigate the undesired effects of the conventional power splitter. In the proposed structure, the power splitter is located between the first and second driver stages to isolate the input node of the power stage from the parasitic components of the power splitter. To verify the feasibility of the proposed structure, we designed conventional and proposed 1.9‐GHz CMOS power amplifiers using 0.11‐µm RF CMOS technology. The measured efficiency and output power of the proposed amplifier are improved compared to those of the conventional amplifier. From the measured results, we successfully verify the feasibility of the proposed split driver stage structure. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2341–2345, 2014

High-Power Transmission Line Transformer Design for Plasma Generators

Efficient and novel design method to implement high-power transmission line transformers (TLTs) that can be used as output balun for plasma generators is presented. The novelty in the presented method involves: the construction of the balun using transmission lines (TLs) in the form of microstrip configuration, which gives higher power handling capacity with larger amount of current and high breakdown voltage, accurate formulation including magnetic design of the balun, such as core selection, flux density, operational current, voltage, and number of turns, and implementation of the balun for radio frequency amplifier section of the plasma generator for the first time. The presented method also integrates Dowell's formulation into microstrip type design and shows that when TLs with rectangular cross sections, such as copper strips, are used for winding, thermal profile of the balun improves since its conductor loss is reduced. Design charts based on analytical formulation to design high-power TLTs are presented. High-power TLT is then constructed, measured, and implemented for 2-MHz plasma generator. All the measurement results, including thermal profile of the TLT and power amplifier performance of the plasma generator at the center frequency, 2 MHz, when the new type of TLT is implemented have been given. It has been shown that the TLT using the design technique presented in this paper can be used as output balun for plasma generators and meet all the requirements of plasma applications.

Hybrid Current-Mode Class-S Power Amplifier With GaN Schottky Diode Using Chip-On-Board Technique for 955 MHz LTE Signal

This paper presents a gallium nitride (GaN)-based hybrid current-mode class-S (CMCS) power amplifier (PA) using a bandpass delta-sigma modulator (BPDSM) for a 955-MHz LTE signal. To enhance the drain efficiency of the CMCS PA, the chip-on-board (COB) technique, which can reduce the external parasitic components of the packaged transistor and allow fast switching operation at high frequencies by minimizing distortion of the pulse waveform, is adopted. Also, GaN Schottky barrier diodes are fabricated in-house to protect the switching transistor against the high negative voltage swing. The differential output filter and balun composed of lumped LC resonators are integrated at the back of the switching transistor to extract amplified LTE signal from the output rectangular waveform, and the fabricated CMCS PA is measured and analyzed at four different states of BPDSM according to the coding efficiency from different input power level to obtain higher power and efficiency. Finally, a cavity bandpass filter (BPF) is added to the output circuit for a more accurate reduction of the harmonics and out-of-band noise signals to enhance system efficiency. From the measured results for an 8.5-dB PAPR 3 G LTE 10-MHz input signal, the proposed CMCS PA has a maximum average output power of 37.61 and 30.78 dBm, and the resulting drain efficiencies of 33.3% and 38.6% with the drain voltage of 19 and 7 V, respectively.

Investigation of Push-Pull Microwave Power Amplifiers Using an Advanced Measurement Setup

In this letter, we investigate the influence of the output balun for realization of wideband and efficient microwave push-pull power amplifiers (PAs). For this, a push-pull GaN-HEMT PA operating between 1-3 GHz without an output balun has been implemented and a novel push-pull harmonic load-pull measurement setup that allows arbitrary balanced fundamental and second harmonic loads to be presented to the push-pull PA is proposed. The measurement results illustrate that the efficiency may be degraded up to 25% if improper common mode harmonic impedances are presented by the balun. The proposed approach allows the PA and balun to be investigated separately and is therefore expected to be an important tool for further research on balun and PA structures suitable for high efficiency and wideband push-pull applications at microwave frequencies.

Integrated CMOS RF transmitter with a single-ended power amplifier

This article presents a highly integrated CMOS RF double-sideband (DSB) transmitter (TX) including an active input balun and a single-ended power amplifier (PA) for a ultrahigh frequency radiofrequency identification (RFID) system-on-chip reader. The conventional TX architecture, including an up-conversion mixer and a balanced PA, requires an output balun to create the needed single-ended load. Compared to the conventional TX architecture, the proposed system provides a more compact circuit and uses a smaller chip area because the active balun and the single-ended PA have a much smaller size than those using a passive balun and a differential PA. In addition, the gain of the active balun, which is generally larger than unity, can be a benefit in the system design budget. The designed TX IC is fabricated using a 0.13 μm CMOS process on a small area of 780 × 560 μm2 (including pads). The TX IC exhibited an overall conversion gain of 41.7 dB, an output P1dB of 18 dBm, an OIP3 of 28 dBm, a DSB noise figure of 14.8 dB, and a power consumption of 284.4 mW, including the 42.9 mW consumed by the local oscillator buffer stages. The implemented TX IC complied with the spectral mask for the DSB amplitude-shift keying signal of the RFID reader at an output power of 15.5 dBm. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:205–210, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27257

A Wideband, Dual-Path, Millimeter-Wave Power Amplifier With 20 dBm Output Power and PAE Above 15% in 130 nm SiGe-BiCMOS

A frequency-scalable, three-stage, transformer-coupled millimeter-wave power amplifier (PA) is implemented in 130 nm SiGe-BiCMOS. Differential common-base gain stages extend collector-emitter breakdown voltage beyond 3 V, while collector-emitter neutralization increases reverse isolation and stability. Monolithic self-shielded transformers designed for low insertion loss and compact dimensions on-chip include: a 2:4 input power splitter, a 4:1 output balun combiner and inter-stage coupling transformers. The balun combiner and fully-differential splitter are compensated for imbalances caused by parasitic interwinding capacitance, and simulations predict better than 3% uniformity between reflected port-to-port impedances at 60 GHz. Simulated impedance uniformity is within 6% from 55-65 GHz, and insertion loss of the 0.015 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> combiner prototypes at 60 GHz is below 1 dB. The 0.72 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> 60 GHz-band PA realizes a measured peak small-signal gain higher than 20 dB with over 10 GHz 3 dB bandwidth. Reverse isolation is better than 51 dB from 50-65 GHz and the PA is unconditionally stable. It consumes 353 mW (quiescent) from a 1.8 V supply and the active area is 0.25 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Maximum output power and peak power-added efficiency (PAE) are 20.1 dBm and 18% at 62 GHz, respectively. An up-banded 79-87.5 GHz PA is also implemented to verify frequency scalability of the design. The 0.23 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area 79 GHz PA prototype produces 18 dBm saturated output power and 9% peak-PAE at 84 GHz from a 2.5 V supply.

A 58–65 GHz Neutralized CMOS Power Amplifier With PAE Above 10% at 1-V Supply

A 60-GHz band, three-stage pseudo-differential power amplifier (PA) is implemented with input and output baluns on-chip. Each stage consists of a neutralized common-source amplifier pair. Neutralization mitigates the intrinsic gate-drain feedback of each transistor for increased power gain and reverse isolation. Shielded transformers couple the gain stages and allow low supply voltage operation. Fabricated in a 65-nm bulk CMOS process, the measured small-signal gain of the 0.13 × 0.41 mm2 PA is 16 dB at 60 GHz with 3-dB bandwidth more than 8.5 GHz, while consuming 50 mW from a 1-V supply. Reverse isolation is better than 42 dB from 55 to 65 GHz. Maximum saturated output power is 11.5 dBm with a peak PAE of 15.2% measured at 62 GHz; from 58 to 65 GHz, the measured PAE is above 10%.

A Fully Integrated 3.3–3.8-GHz Power Amplifier With Autotransformer Balun

This paper demonstrates the usage of a differential autotransformer as an output balun for an integrated power amplifier (PA) operating at low-gigahertz frequencies. In comparison with a conventional transformer balun, an autotransformer balun offers lower power losses, thereby increasing the saturated output power and reducing the gain compression at the edge of target power range. A theoretical analysis of an integrated autotransformer is given, comparison with a magnetic transformer is performed. The concept was experimentally verified in a fully integrated PA for a 3.3-3.8-GHz WiMAX band fabricated in SiGe : C bipolar technology. The active part of the amplifier implements the derivative superposition method aimed at linearizing the power transfer characteristic. Measured PA delivers saturated output power above 29 dBm. The maximum achieved power-added efficiency exceeds 40% at 3.4 GHz. At 3.5 GHz, 1-dB gain compression occurs for P out = 24.6 dBm.