Abstract
This paper proposes a design methodology for multi-octave planar push–pull power amplifiers (PPPAs) to tackle the challenges associated with the integration of planar balanced to unbalanced transformers (baluns) with packaged transistors characterized by significant parasitics. This methodology relies on carefully selecting the balun’s placement and adding external matching networks to separately control the odd- and even-mode impedances presented to the power amplifier (PA) to ensure high-efficiency operation over a broad range of frequencies. Proper second harmonic impedances are obtained by placing the balun in close proximity to the transistors’ terminals and repurposing the packaged transistors’ leads into a coupled-line with a high coupling coefficient. Furthermore, adequate odd-mode terminations are realized using broadband matching networks at the unbalanced side of the baluns. Following this methodology, an 85-W PPPA was designed using off-the-shelf packaged gallium–nitride high electron-mobility transistors. The fabricated PA demonstrated drain efficiency and output power above 45% and 46.5 dBm, respectively, over the frequency band spanning from 0.45 to 1.95 GHz. Furthermore, the fabricated PA was successfully linearized using digital predistortion when driven with single- and multi-band modulated signals. Overall, the fabricated PA had the best reported power, efficiency, bandwidth, and second harmonic rejection combination for a multi-octave PPPA designed with input and output baluns using packaged off-the-shelf transistors.
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