Abstract
A V-band power amplifier in a bulk 65nm CMOS technology with a peak gain 14.5dB and 3-dB bandwidth of 28.8GHz (50.8–79.6GHz) is presented. The techniques to boost bandwidth and power efficiency are presented. In addition, the design of dummy filling to satisfy manufacturing density requirements while having negligible effects on performances is discussed in details. The PA features a three stage transformer coupled differential architecture with integrated input and output baluns on-chip. The PA achieves a measured saturated output power of 15.1dBm and output 1dB compression power of 12.9dBm at 65GHz. The peak power-added efficiency is 18.9%. The entire PA occupies area of 0.31mm2, while consuming 150mW from a 1.25V supply.
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