Orders Of Magnitude Lower Leakage Research Articles

High‐Temperature High‐Energy‐Density Dielectric Polymer Nanocomposites Utilizing Inorganic Core–Shell Nanostructured Nanofillers

AbstractHigh‐energy‐density polymer dielectrics capable of high temperature operation are highly demanded in advanced electronics and power systems. Here, the polyetherimide (PEI) composites filled with the core–shell structured nanoparticles composed of ZrO2 core and Al2O3 shell are described. The establishment of a gradient of the dielectric constants from ZrO2 core and Al2O3 shell to PEI matrix gives rise to much less distortion of the electric field around the nanoparticles, and consequently, high breakdown strength at varied temperatures. The wide bandgap Al2O3 shell creates deep traps in the composites and thus yields an order of magnitude lower leakage of current density of the composites with respect to those with pristine ZrO2 at high temperatures. Accordingly, the composite delivers a discharged energy density of 5.19 J cm−3 and 150 °C, which outperforms the current free‐standing high‐temperature dielectric polymer and polymer composite films measured at 10 Hz. Moreover, the core–shell structured composites endow great thermal stability, charge–discharge efficiency, and the improved energy density with increasing temperature from 25 to 150 °C. The finite element simulations and numerical calculations are performed to reveal the mechanistic impacts of the core–shell structure on the electric field distribution and electrical conduction of the composites.

Lead-free relaxor thin films with huge energy density and low loss for high temperature applications

We report record energy storage density (>80 J cm−3) in Pb-free relaxor ferroelectrics based on Mn-doped BiFeO3–BaTiO3 thin films. Rapid interval deposition was used to impose layer-by-layer growth improving crystallinity and lowering unwanted defects concentration. The growth and Mn doping produced an order of magnitude lower leakage, with strongly reduced dielectric loss (from room temperature to >300 °C, and 100 Hz to 1 MHz), e.g. by a factor of 5 at 225 °C and 25 kHz. At room temperature (RT), the dielectric breakdown strength increased by a factor of 1.5 to >3000 kV cm−1 while the dielectric constant remained flat, at ~1000 from RT to 350 °C. The films perform better than competing materials (e.g. PZT and SrTiO3-based) while being Pb-free and while operating up to 350 °C, which SrTiO3-based systems do not. Our work gives considerable promise for high energy and power density capacitors for harsh environments.

Heteroepitaxial Pb0.9Sr0.1TiO3/Bi0.9La0.1FeO3/Pb0.9Sr0.1TiO3 multiferroic structure: an effective way to improve the electrical, ferroelectric and magnetic performance

A ferroelectric/multiferroic structure composed of (Pb0.9Sr0.1)TiO3 (PST) and (Bi0.9La0.1)FeO3 (BLF) was heteroepitaxially deposited on a LaNiO3 buffered (001) SrTiO3 substrate by pulse laser deposition. Interestingly, the PST layer was acting as a buffering layer between BLF and electrode to suppress the migration of free carries in the heterostructure. A well-grown crystalline dense structure was observed from the surface morphology of PST/BLF/PST heterostructure. Moreover, the PST/BLF/PST trilayer exhibited improved ferroelectric and dielectric behaviors, together with two orders of magnitude lower leakage current and higher dielectric constant. Our result indicate that the multiferroic PST/BLF/PST heterostructure may have a promising application for the future high-density memory.

Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology

With the emergence of nonplanar CMOS devices at the 22-nm node and beyond, it is highly likely that multigate device adoption will occur in a high-performance process technology, owing to the increased performance and area benefits. In this paper, for the first time, we evaluate symmetric (Symm-Φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) and asymmetric (Asymm-Φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) gate-workfunction FinFETs head to head in a high-performance process, using technology computer-aided design 3-D device simulations. We demonstrate that Asymm-Φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> shorted-gate (a-SG) n/p-FinFETs, which use both workfunctions corresponding to typical high-performance metal-gate n/p-FinFETs, are promising, as they can yield over two orders of magnitude lower leakage without excessive degradation in ON-state current, in comparison to Symm- ΦG shorted-gate (SG) FinFETs, placing them in a better position than back-gate biased independent-gate (IG) FinFETs for leakage reduction. Thereafter, we explore the design space of FinFET logic gates, latches, and flip-flops, for optimal tradeoffs in leakage versus delay and temperature, using mixed-mode 2-D device simulations. Elementary logic gates (such as INV, NAND2, NOR2, XOR2, and XNOR2) using Asymm-Φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> SG-mode FinFETs appear to be located optimally in the leakage-delay spectrum, in comparison to the most versatile configurations possible by mixing corresponding Symm-Φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> SG- and IG-mode FinFETs. Latches and flip-flops, however, require an astute combination of Symm-Φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> and Asymm-Φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> FinFETs to optimize leakage, delay, and setup time simultaneously.

Damage Effects in Boron and BF 2 Ion‐Implanted p+‐n Junctions in Silicon

Boron‐ and p+‐n junctions are compared. At 50V reverse bias diodes, fabricated in <100> silicon and annealed in a wet atmosphere, typically exhibited two orders of magnitude lower leakage than B‐implanted diodes on the same wafer. The improved reverse I–V characteristics of the junctions are related to the implant damage. Excessive leakage current in B‐implanted diodes is correlated with oxidation‐induced defects using scanning electron microscopy. Argon damage implant experiments indicate that an amorphous surface region caused by the implant prevents the propagation of defects into the junction region during anneal in a wet oxygen atmosphere.