Optimum Noise Performance Research Articles

Threshold bounce — occupancy-dependent modulation of the discriminating threshold in silicon detectors

The front-end electronics of silicon detectors are typically designed to ensure optimal noise performance for the expected input charge. A combination of preamplifiers and shaper circuits result in a nontrivial response of the front-end to injected charge, and the magnitude of the response may be sizeable in readout windows subsequent to that in which the charge was initially injected. The modulation of the discriminator threshold due to the superposition of the front-end response across multiple readout windows is coined “threshold bounce”. In this paper, we report a measurement of threshold bounce using silicon modules built for the Phase-II Upgrade of the ATLAS detector at the Large Hadron Collider. These modules utilize ATLAS Binary Chips for their hit readout. The measurement was performed using a micro-focused 15 keV photon beam at the Diamond Light Source synchrotron. The effect of the choice of photon flux and discriminator threshold on the magnitude of the threshold bounce is studied. A Monte Carlo simulation which accounts for the front-end behaviour of the silicon modules is developed, and its predicted hit efficiency is found to be in good agreement with the measured hit efficiency.

RF-SOI Low-Noise Amplifier Using RC Feedback and Series Inductive-Peaking Techniques for 5G New Radio Application.

This paper presents a low-noise amplifier (LNA) with an integrated input and output matching network designed using RF-SOI technology. This LNA was designed with a resistive feedback topology and an inductive peaking technology to provide 600 MHz of bandwidth in the N79 band (4.4 GHz to 5.0 GHz). Generally, the resistive feedback structure used in broadband applications allows the input and output impedance to be made to satisfy the broadband conditions through low-impedance feedback. However, feedback impedance for excessive broadband characteristics can degrade the noise performance as a consequence. To achieve a better noise performance for a bandwidth of 600 MHz, the paper provided an optimized noise performance by selecting the feedback resistor value optimized for the N79 band. Additionally, an inductive peaking technique was applied to the designed low-noise amplifier to achieve a better optimized output matching network. The designed low-noise amplifier simulated a gain of 20.68 dB and 19.94 dB from 4.4 to 5.0 GHz, with noise figures of 1.57 dB and 1.73 dB, respectively. The input and output matching networks were also integrated, and the power consumption was designed to be 9.95 mA at a supply voltage of 1.2 V.

An artificial bridge circuit approach between two biological neurons using nanoscale topologies towards paralytic disorders

The advent of Nanoscale IC technology towards pulse-based neural systems reactivates the dead nervous about restoring the functionality of paralytic disorders. This work reports in first time a design of a novel CMOS biological neuron system, which replaces a dead neuron between two neurons to restore communication in paralyzed individuals. The work binds into three stages: design of a spiking leaky Integrator and Fire (LIF) neuron with refractory period mechanisms, which achieves a low power consumption of 2.4 μW, in the first stage; an adaptive homeostatic synapse with short and long-term spike plasticity, that reconfigure the spiking neuron networks of multichannel sensor electrodes to record the electric signal from the active cell as second stage; the final stage presents a low-power common source current reuse regulated cascode (CS-CR-RGC) TIA for amplifying the weak synapse current signal, which achieves a high gain of 135.71 dBΩ with an optimized noise performance of 0.19 pA/Hz. The entire work is designed and implemented using a CMOS 65 nm commercial process that occupies a die area of 400 μm × 120 μm.

Chip-Level GHz Capable Balanced Quantum Homodyne Receivers

We present a design of balanced homodyne receivers suitable for ultra-low noise quantum applications such as continuous-variable quantum key distribution and quantum random number generation. For best noise and bandwidth performance a die-level low-parasitic photodiode together with a low-noise high-speed transimpedance amplifier are explored together with a planar lightwave circuit splitter chip serving as a photomixer. Bandwidths of 750 MHz and 2.6 GHz were accomplished while maintaining optimum noise performance, as evidenced by very high quantum-to-classical noise ratios of 26.8 and 18.6 dB, respectively. A common-mode rejection ratio of at least 40 dB was achieved for a frequency range of up to 1 GHz. Its application for continuous-variable quantum key distribution was evaluated by means of estimations under a strict untrusted receiver assumption, showing its potential for generating up to 43 Mbit/s secure-key rate over a reach of 10 km, whereas up to 100 Mbit/s could be supported at shorter reaches. Moreover, the high quantum-to-classical clearance values can enable high quality quantum random number generation at Gb/s rates. The multi-purpose operation of the designed balanced receivers for classical communications was examined showing reception sensitivities of −55.8 and −52.6 dBm at 500 Mbit/s and 1 Gbit/s quadrature phase shift keying transmission, respectively, using the 750 MHz receiver. The faster 2.6 GHz receiver enabled 10 Gbit/s duobinary transmission at −14.8 dBm sensitivity.

CMOS-Driven VCSEL-Based Photonic Links: an Exploration of the Power-Sensitivity Trade-Off

This article explores the power-sensitivity trade-off in optical receivers aiming to improve the energy-efficiency of the overall link. Optical receivers with field-effect transistor (FET) front-ends (FEs) are usually designed for optimal noise performance by matching the circuit&#x2019;s input capacitance (<i>C_I</i>) to the total input parasitic capacitance (<i>C_D</i>). However, the receiver&#x2019;s power dissipation is also proportional to the input capacitance <i>C_I</i>. Therefore, this paper studies the feasibility of the capacitive matching rule in the context of minimizing the power dissipation of the overall link. For that purpose, design trade-offs for the receiver, transmitter, and the overall link are presented. Comparisons are made to study how much the receiver can be downsized, sacrificing optimal noise performance, before its power reduction is offset by the transmitter&#x2019;s increase in power. Simulation results show that energy-efficient links require low-power receivers with input capacitance much smaller than that required for noise-optimum performance. As an example, for a 25 Gb/s operation, an optical loss budget of 12.6 dB, and a receiver designed in 65 nm CMOS technology with <i>C_D</i> of 200 fF, the overall link dissipates 2.55 pJ/bit when the receiver&#x2019;s noise is minimized, leading to a receiver with <i>C_I</i>/<i>C_D</i> = 1.29. When optimized for overall link efficiency, the receiver size is significantly reduced to <i>C_I</i>/<i>C_D</i> = 0.38 and the link&#x2019;s energy-efficiency also improves to 1.41 pJ/bit. If the link budget or knowledge of the transmitter side is incomplete, our analysis indicates that maximizing gain with value of <i>C_I</i>/<i>C_D</i> = 0.5 is a reasonable choice.

Bias dependent physics-based model of low-frequency noise for nanowire type gate-all-around MOSFETs

In this study, the bias dependence of low-frequency noise (LFN) in nanowire type gate-all-around (GAA) MOSFETs was physically modeled. In the model, the inversion carrier density distribution was considered based on the potential in the channel that changes according to the bias. The developed model was verified with measurement data of the fabricated device. The model could help circuit designers to optimize noise performance in analog/RF applications when designing integrated circuits using nanowire-type GAA MOSFETs.

(Invited) Impact of Processing Factors on the Low-Frequency Noise of Gate-All-Around Silicon Vertical Nanowire FETs

This paper gives an overview of the impact of certain processing steps on the low-frequency (LF) noise behavior of silicon Gate-All-Around (GAA) Vertical Nanowire (VNW) MOS transistors. It is shown that the width of a Replacement Metal Gate (RMG) cap impacts the flicker noise Power Spectral Density (PSD). The type of source contact, i.e., bulk versus a confined top contact significantly changes the nature and the magnitude of the 1/f noise. Finally, the doping density of the silicon nanowires has a subtle influence, whereby the dominant fluctuation mechanism shifts from number to mobility fluctuations, while increasing the doping density. Optimal noise performance is achieved for intermediate in-situ nanowire B doping density.

A 61.2-dBΩ, 100 Gb/s Ultra-Low Noise Graphene TIA over D-Band Performance for 5G Optical Front-End Receiver

This work reports in first time a 100-Gb/s, ultra-low noise, variable gain multi-stagger tuned transimpedance amplifier (VGMST-TIA) over the D-band performance. The whole work is binding into two phases. The first phase involves the modeling and characterization of graphene field-effect transistor (GFET) with an optimized transition frequency of operation. While in the second phase, a TIA design employs a T-shaped symmetrical L-R network at the input, which mitigates the effect of photo diode capacitance and achieves a D-band of operation. The proposed work uses a VGMST to establish TIA, which realizes optimum noise performance. The high gain 3-stage VGMST-TIA effectively minimizes the white noise and illustrates a sharp out-of-band roll-off to achieve considerable noise reduction at high frequencies. The active feedback mechanism controls the transimpedance gain by tuning the control voltage which results better group delay. Besides, an L-C circuit is employed at the output to enhance bandwidth. The full TIA is implemented and fabricated using a commercial nano-manufacturing 9-nm graphene film FET on a silicon wafer using 0.065-μm process. The TIA achieves a flat transimpedance gain of 61.2 dBΩ with ± 9 ps group delay variation over the entire bandwidth. The proposed TIA measured an impedance bandwidth of 0.2 THz with ultra-low input-referred noise current density of 2.03 pA/√Hz. The TIA supports a 100-Gb/s data transmission due to large bandwidth; therefore, a bit-error-rate (BER) less than 10−12 is achieved. The chip occupies an area of 0.92 * 1.34 mm2 while consuming power of 21 mW under supply of 1.8 V.

Optimizing the Noise Performance of Multielectrode Image Charge Detectors Constructed on Printed Circuit Boards

In image charge sensing applications, a tradeoff exists between minimizing detector capacitance for improved amplifier noise performance and adding repeated sensing stages for noise improvement through averaging of repeated signals. In order to understand this tradeoff, the link between image charge detector geometry and capacitance is studied through finite element analysis. This knowledge is then used to present a novel method for determining the relevant detector parameters such that the system noise performance for a given amplifier is optimized. This method is independent of specific amplifier parameters. We find that the optimum noise performance does not lie in simply arbitrarily increasing the number of sensing stages, but depends on the amount of parasitic input capacitance to the amplifier. The greater the parasitic capacitance, the greater the number of stages for the optimum detector. The optimum number of stages is also highly dependent on the detector geometry.

Design and analysis of a wideband compact LNA-mixer in millimeter wave frequency

This paper presents the design and analysis of a millimeter-wave LNA-mixer, which adopts a low-noise single-to-differential conversion balun with low phase (gain) imbalance, using a common-source and a common-gate stage. Each stage employs a cascode transistor with inductors in the gate and source for improving noise, gain, and bandwidth performance. A new transformer-based network is proposed for broadband input matching. Also, a transformer network couples between transconductance and switching stage for independent biasing of two stages, which provides passive gain without extra power consumption and further noise reduction. To optimize the size of transistors and their current density, a new figure of merit is utilized which concurrently optimize noise performance, cut-off frequency, and transconductance efficiency. The input frequency range is 27.5–43.5 GHz with typical input signal power of – 40 dBm and a switching signal power of 0dBm, using 0.18 µm CMOS technology. The simulation result shows that typical conversion gain is 24–27 dB, DSB-NF is 5.33–9.1 dB, and third-order intercept point is − 7.83 dBm. The DC power consumption is 11.13 mW with a chip size of 0.45 mm2.

A numerical study on the sound transmission loss of HST aluminum extruded panel

Aluminum is a light, strong, and corrosion-resistant material. Its extruded form, the aluminum extruded panel, consists of two aluminum plates with truss core, which can be applied in a wide range of engineering areas. In this work, the structure-acoustic coupling finite element method (FEM) is employed to analyze the sound transmission through high-speed train (HST) aluminum extruded panels. The automatically matched layer (AML) is used to simulate the non-reflective boundary condition. It is found that the predicted sound transmission loss (STL) is in good agreement with the experimental results and the prediction accuracy of the finite element method can be further verified. Based on this proposed method, a parametric study is carried out to investigate how the structure parameters affect the STL. The results suggest that the rib angle exhibits a greater effect on STL in the above-middle frequency area where the modal density is high. The increase in the height between the panels will lead to a higher STL overall value of the aluminum extruded panel and make the STL dips move toward higher frequencies, while the increase of the rib thickness will drive the STL dips to an opposite direction. Finally, the STLs of the aluminum extruded panel in different regions of the train body are comprehensively analyzed. The highest overall value of STL is found in the flat-top region, whereas the lowest value appears in the curve-top region. Overall, the results in this article can provide valuable implications for the noise performance optimization of HST.

Special Issue No. – 10, June, 2020 Journal &gt; Special Issue &gt; Special Issue No. – 10, June, 2020 &gt; Page 5 “Quantative Methods in Modern Science” organized by Academic Paper Ltd, Russia MORPHOLOGICAL AND ANATOMICAL FEATURES OF THE GENUS GAGEA SALISB., GROWING IN THE EAST KAZAKHSTAN REGION Authors: Zhamal T. Igissinova,Almash A. Kitapbayeva,Anargul S. Sharipkhanova,Alexander L. Vorobyev,Svetlana F. Kolosova,Zhanat

Special Issue No. – 10, June, 2020 Journal &gt; Special Issue &gt; Special Issue No. – 10, June, 2020 &gt; Page 5 “Quantative Methods in Modern Science” organized by Academic Paper Ltd, Russia MORPHOLOGICAL AND ANATOMICAL FEATURES OF THE GENUS GAGEA SALISB., GROWING IN THE EAST KAZAKHSTAN REGION Authors: Zhamal T. Igissinova,Almash A. Kitapbayeva,Anargul S. Sharipkhanova,Alexander L. Vorobyev,Svetlana F. Kolosova,Zhanat

Multi-Rate Low-Noise Optical Receiver Front-End

Conventional optical receivers are mostly optimized for single data rate. In this work, after examining conventional optical front-ends, we present the low-noise tunable front-end (LNTF) topology, which is able to achieve optimized noise performance at multiple data rates. In addition, colored noise optimization techniques including capacitive noise scaling and CMOS inverter based transimpedance amplifier (TIA) are also studied, which together with the LNTF form a low-noise design methodology for silicon photonics based CMOS optical receiver. Employing these techniques, the implemented 3D hybrid-integrated silicon photonics receiver achieves excellent noise performance of 0.91 μArms and 0.5 μArms input-referred noise current at 25 and 10 Gb/s, respectively, which enables high sensitivity of −14.6 dBm and −16.5 dBm OMA at BER = 10−12, correspondingly.

A 0.6-µW Chopper Amplifier Using a Noise-Efficient DC Servo Loop and Squeezed-Inverter Stage for Power-Efficient Biopotential Sensing.

To realize an ultra-low-power and low-noise instrumentation amplifier (IA) for neural and biopotential signal sensing, we investigate two design techniques. The first technique uses a noise-efficient DC servo loop (DSL), which has been shown to be a high noise contributor. The proposed approach offers several advantages: (i) both the electrode offset and the input offset are rejected, (ii) a large capacitor is not needed in the DSL, (iii) by removing the charge dividing effect, the input-referred noise (IRN) is reduced, (iv) the noise from the DSL is further reduced by the gain of the first stage and by the transconductance ratio, and (v) the proposed DSL allows interfacing with a squeezed-inverter (SQI) stage. The proposed technique reduces the noise from the DSL to 12.5% of the overall noise. The second technique is to optimize noise performance using an SQI stage. Because the SQI stage is biased at a saturation limit of 2VDSAT, the bias current can be increased to reduce noise while maintaining low power consumption. The challenge of handling the mismatch in the SQI stage is addressed using a shared common-mode feedback (CMFB) loop, which achieves a common-mode rejection ratio (CMRR) of 105 dB. Using the proposed technique, a capacitively-coupled chopper instrumentation amplifier (CCIA) was fabricated using a 0.18-µm CMOS process. The measured result of the CCIA shows a relatively low noise density of 88 nV/rtHz and an integrated noise of 1.5 µVrms. These results correspond to a favorable noise efficiency factor (NEF) of 5.9 and a power efficiency factor (PEF) of 11.4.

The Ultimate Noise Limit for Hall Plates in Voltage, Current, and Hybrid Operating Modes

If Hall plates are used as magnetic field sensors they are usually powered up by a current source connected to a pair of non-neighboring contacts. The output voltage is tapped at another pair of non-neighboring contacts. In this paper we study more general operating conditions of Hall plates with an arbitrary number of contacts. In such hybrid operating modes current sources are connected to a first set of contacts and voltage sources to a second set of contacts. Output voltages are tapped at the first set of contacts and output currents are measured at the second set of contacts. All these output signals are multiplied by coefficients and added up. The purpose of this work is to figure out which operating mode and which Hall plate achieve maximum signal at minimum thermal noise and power dissipation. To this end we develop a theory, which gives the ratio of signal over noise and power as a function of the resistance matrix of Hall plates, of the supply voltages and currents, and of the coefficients. Optimization is done analytically in closed form and numerically for specific examples. The results are: 1) all operating modes have identical noise performance if their parameters are optimized; 2) for any Hall plate one can measure its resistance matrix and insert its values into our formulae to obtain the optimum supply currents and coefficients for optimum noise performance.

A new gm-boosting design technique for wideband inductorless low-noise transconductance amplifiers

In this paper, a new gm-boosting design technique for wideband inductorless low-noise transconductance amplifiers (LNTA) is presented, resulting in optimal input matching, and noise and linearity performance. The proposed technique in its basic form, relaxes the constraint on transconductance value of conventional gm-boosted common-gate LNTAs so that the overall transconductance can be selected regardless of input matching condition. In addition, the technique can be reconfigured for either optimum noise performance or linearity improvement while imposing negligible power and area overhead. Analytical derivation and practical design procedure for both task is thoroughly discussed. Implemented in a standard 0.18 μm CMOS process, for a reasonable power consumption of 6.7 mW, the proposed LNTA achieves about 24 mS transconductance and a minimum NF of 3.4 dB over a bandwidth of 0.4–2.1 GHz.

Low-Noise Schottky Junction Trigate Silicon Nanowire Field-Effect Transistor for Charge Sensing

Silicon nanowire (SiNW) field-effect transistors (SiNWFETs) are of great potential as a high-sensitivity charge sensor. The signal-to-noise ratio (SNR) of an SiNWFET sensor is ultimately limited by the intrinsic device noise generated by carrier trapping/detrapping processes at the gate oxide/silicon interface. This carrier trapping/detrapping-induced noise can be significantly reduced by replacing the noisy oxide/silicon interface with a Schottky junction gate (SJG) on the top of the SiNW. In this paper, we present a tri-SJG SiNWFET (Tri-SJGFET) with the SJG formed on both the top surface and the two sidewalls of the SiNW so as to enhance the gate control over the SiNW channel. Both experiment and simulation confirm that the additional sidewall gates in a narrow Tri-SJGFET indeed can confine the conduction path within the bulk of the SiNW channel away from the interfaces and significantly improve the immunity to the traps at the bottom buried oxide/silicon interface. Therefore, the optimal low-frequency noise performance can be achieved without the need for any substrate bias. This new gating structure holds promises for further development of robust SiNWFET-based charge sensors with low noise and low operation voltage.

A constant loop bandwidth in delta sigma fractional-N PLL frequency synthesizer with phase noise cancellation

This work presents the design of a new and unique design technique of constant loop bandwidth and phase-noise cancellation in a wideband ΔΣ fractional-N PLL frequency synthesizer. Phase noise performance of the proposed ΔΣ fractional-N PLL frequency synthesizer has been verified using CppSim simulator with the help of transistor level simulation results in Cadence SpecctreRF. Transient response of the proposed ΔΣ fractional-N PLL has been verified in transistor level simulation using Cadence SpectreRF in 0.13 μm standard CMOS process. The proposed phase-noise cancellation and constant loop bandwidth in wideband ΔΣ fractional-N PLL reduces the out of band phase noise by 18 dBc/Hz at 2 MHz offset frequency for a closed loop bandwidth of 1 MHz, when ICP,max is equal to 2.6 mA. PLL locking time has been reduced with phase-noise cancellation and a constant loop bandwidth calibration circuits using the proposed CP unit current cell for the mismatch compensated PFD/DAC in wideband ΔΣ fractional-N PLL frequency synthesizer. Optimum phase noise performance can be achieved with the help of proposed design technique. Proposed ΔΣ fractional-N PLL frequency synthesizer is locked within 14.0 μs with an automatic frequency control circuit of the LC VCO and a constant loop bandwidth calibration circuit through the use of proposed CP unit current cell for the mismatch compensated PFD/DAC for the phase-noise cancellation in worst case condition of KVFC = 10 and KLBC = 150. Our new design technique can be extensively integrated for wideband fractional-N PLL for new type of wireless communication paradigm using the thinnest channel subharmonic transistor and low power devices, and it has the potential to open a new era of fractional-N PLLs for wideband application.

Low phase-noise oscillator based on SIW bandpass filter implementing at the Qsc-peak frequency

ABSTRACTIn this paper, a novel low phase-noise oscillator employing an substrate integrated waveguide (SIW) bandpass filter (BPF) embedded with a complementary spiral resonator (CSR) is proposed. The Qsc-peak frequency is chosen for the design of the oscillator to achieve optimal phase noise performance. The CSR exited by TM01 mode has been etched on the top metal of the circular cavity. Three transmission poles and three transmission zeros can be obtained by the proposed SIW BPF which is regarded as the frequency stabilization element. Meanwhile, a short summary about how to obtain a high Qsc-factor to achieve low phase noise performance has been illustrated. A C-band oscillator using a field effect transistor has been designed and experimentally demonstrated at 5.71 GHz with a 147.6 dBc/Hz phase noise at 1 MHz offset frequency. Moreover, the output power is −1.49 dBm with a figure of merit of −209.2 dBc/Hz and less than −32.8 dBm spurious harmonics is obtained.

A chemical shift encoding (CSE) approach for spectral selection in fluorine-19 MRI.

To develop a chemical shift encoding (CSE) approach for fluorine-19 MRI of perfluorocarbons in the presence of multiple known fluorinated chemical species. A multi-echo CSE technique is applied for spectral separation of the perfluorocarbon perfluoro-15-crown-5-ether (PFCE) and isoflurane (ISO) based on their chemical shifts at 4.7 T. Cramér-Rao lower bound analysis is used to identify echo combinations with optimal signal-to-noise performance. Signal contributions are fit with a multispectral fluorine signal model using a non-linear least squares estimation reconstruction directly from k-space data. This CSE approach is tested in fluorine-19 phantoms and in a mouse with a 2D and 3D spoiled gradient-echo acquisition using multiple echo times determined from Cramér-Rao lower bound analysis. Cramér-Rao lower bound analysis for PFCE and ISO separation shows signal-to-noise performance is maximized with a 0.33 ms echo separation. A linear behavior (R2 = 0.987) between PFCE signal and known relative PFCE volume is observed in CSE reconstructed images using a mixed PFCE/ISO phantom. Effective spatial and spectral separation of PFCE and ISO is shown in phantoms and in vivo. Feasibility of a gradient-echo CSE acquisition and image reconstruction approach with optimized noise performance is demonstrated through fluorine-19 MRI of PFCE with effective removal of ISO signal contributions. Magn Reson Med 79:2183-2189, 2018. © 2017 International Society for Magnetic Resonance in Medicine.