Flow Design Optimization Research Articles

A Modified ABC Algorithm & Its Application to Wireless Sensor Network Dynamic Deployment

Wireless Sensor Networks plays a gargantuan role in instrumenting the modern day world; hence it is crucial to develop an optimal design flow. Out of the various Swarm intelligent algorithms developed so far, Artificial Bee Colony (ABC) algorithm offers a vivid scope for this objective. First introduced for solving numerical optimization problems, ABC has now spread across almost every phase of WSN construction. In this study, an improved ABC algorithm has been proposed to match the different characteristics of wireless sensor network deployment process, which will be optimum for real time dynamic network functioning. KEYWORDS: Wireless Sensor Networks, Swarm Intelligent Algorithms, scouts, foragers, onlookers, waggle dance, self organization, Opposition-based learning.

Cost Optimization Method of Large-scale Prestressed Wire Winded Framework on Multiple-island Genetic Algorithm

Prestressed wire winded framework (PWWF) is an advanced structure and the most expensive part in the large-scale equipment. The traditional design of PWWF is complicated, highly iterative and cost uncontrolable, because PWWF is a variable stiffness multi-agent structure, with non-linear loading and deformation coordination. In this paper, cost optimization method of large-scale PWWF by multiple-island genetic algorithm (MIGA) is presented. Optimization design flow and optimization model are proposed based on variable-tension wire winding theory. An example of the PWWF cost optimization of isostatic equipment with axial load 6 000 kN is given. The optimization cost is reduced by 21.6% compared with traditional design. It has also been verified by the finite-element analysis and successfully applied to an actual PWWF design of isostatic press. The results show that this method is efficient and reliable. This method can also provide a guide for optimal design for ultra-large dimension muti-frame structure of 546 MN and 907 MN isostatic press equipment.

Dimension Optimization Design of the Stewart Platform in FAST

China is now building the largest single dish radio telescope in the world in Guizhou province, which is called Five-hundred meter Aperture Spherical radio Telescope (FAST). A Stewart platform is introduced in FAST as an accuracy adjustable mechanism for feed receivers. The main purpose of this paper is to discuss dimension optimization design method of the Stewart platform based on three optimization objective functions. The optimization objective functions can reflect the operability and accuracy of the Stewart platform, and optimization design flow is presented according to the important degree of the three optimization objectives. Finally, a set of optimized parameters is obtained, and the study in this paper provides a basis for the coming optimization the feed support system for FAST in the next step.

Reduced order model assisted evolutionary algorithms for multi-objective flow design optimization

Evolutionary algorithms (EAs) have been widely used for flow design optimization problems for their well-known robustness and derivative-free property as well as their advantages in dealing with multi-objective optimization problems and providing global optimal solutions. However, EAs usually involve a large number of function evaluations that are sometimes quite time consuming. In this article a reduced order modelling technique that combines proper orthogonal decomposition and radial basis function interpolation is developed to reduce the computational cost. These models provide an efficient way to simulate the whole flow region with varied geometry parameters instead of solving partial differential equations. As a test case, the design optimization of a heat exchanger is considered. Shape variation is conducted through a free form deformation technique, which deforms the computational grid employed by the flow solver. A comparison between the optimization results when using reduced order models and the exact flow solver is presented.

Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology

We propose a design optimization flow for a high-speed and low-power operational transconductance amplifier (OTA) using a gm/ID lookup table design methodology in scaled CMOS. This methodology advantages from using gm/ID as a primary design parameter to consider all operation regions including strong, moderate, and weak inversion regions, and enables the lowest power design. SPICE-based lookup table approach is employed to optimize the operation region specified by the gm/ID with sufficient accuracy for short-channel transistors. The optimized design flow features 1) a proposal of the worst-case design scenario for specification and gm/ID lookup table generations from worst-case SPICE simulations, 2) an optimization procedure accomplished by the combination of analytical and simulation-based approaches in order to eliminate tweaking of circuit parameters, and 3) an additional use of gm/ID subplots to take second-order effects into account. A gain-boosted folded-cascode OTA for a switched capacitor circuit is adopted as a target topology to explore the effectiveness of the proposed design methodology for a circuit with complex topology. Analytical expressions of the gain-boosted folded-cascode OTA in terms of DC gain, frequency response and output noise are presented, and detailed optimization of gm/IDs as well as circuit parameters are illustrated. The optimization flow is verified for the application to a residue amplifier in a 10-bit 125MS/s pipeline A/D converter implemented in a 0.18µm CMOS technology. The optimized circuit satisfies the required specification for all corner simulations without additional tweaking of circuit parameters. We finally explore the possibility of applying this design methodology as a technology migration tool, and illustrate the failure analysis by comparing the differences in the gm/ID characteristics.

Accurate, Pre-RTL Temperature-Aware Design Using a Parameterized, Geometric Thermal Model

Preventing silicon chips from negative, even disastrous thermal hazards has become increasingly challenging these days; considering thermal effects early in the design cycle is thus required. To achieve this, an accurate yet fast temperature model together with an early-stage, thermally optimized, design flow are needed. In this paper, we present an improved block-based compact thermal model (HotSpot 4.0) that automatically achieves good accuracy even under extreme conditions. The model has been extensively validated with detailed finite-element thermal simulation tools. We also show that properly modeling package components and applying the right boundary conditions are crucial to making full-chip thermal models like HotSpot accurately resemble what happens in the real world. Ignoring or over-simplifying package components can lead to inaccurate temperature estimations and potential thermal hazards that are costly to fix in later designs stages. Such a full-chip and package thermal model can then be incorporated into a thermally optimized design flow where it acts as an efficient communication medium among computer architects, circuit designers and package designers in early microprocessor design stages, to achieve early and accurate design decisions and also faster design convergence. For example, the temperature-leakage interaction can be readily analyzed within such a design flow to predict potential thermal hazards such as thermal runaway.

Information modeling and reengineering for product development process

Design process is an important stage in product development. Information model is a useful tool in analyzing and improving complex design process. It can facilitate to rebuild the process through visualizing information flow. Owing to the disadvantages of describing complex design process with data flow diagram (DFD), the extended DFD with powerful description ability is put forward. After the extended DFD is transformed into information model, the present optimal design flow is evaluated and mapped to design structure matrix (DSM). Based on DSM, the reengineering of design process can help manage tasks in concurrent design process. Interpretative structural modeling (ISM) method is adopted to realize the partitioning programming of DSM. Grey theory and work transformation matrix (WTM) are used to find new sequence of the coupled block. Eventually, one case study is employed to illustrate the method and the result validates that it can shorten the time and guarantees the quality and function of design process.

NUMERICAL SIMULATION AND EXPERIMENT STUDY FOR TURBULENT FLOW IN THE IMPELLER OF CENTRIFUGAL PUMP

The internal flow between the impellers of IH65 centrifugal pump is investigated.Based on the Reynolds-aver- aging N-S equations and standard k-etwo-equation turbulent model,the simulations of turbulent flow between the impellers are performed by usin8 the flow computing software Fluent under different operating conditions.The calculation results are compared with the experimental data by particle image veloci- meter(PIV).Based on the analysis of the calculated results of velocity and pressure profiles in the centrifugal pump and ex- perimentally observed phenomenon of flow impact,secondary flow and recirculation,some design improvements are proposed, which give suggestions on the optimal design and internal two-phase flow study of the centrifugal pump.

Optimal Integer Delay-Budget Assignment on Directed Acyclic Graphs

Excess delay that each component of a design can tolerate under a given timing constraint is referred to as delay budget. Delay budgeting has been widely exploited to improve the design quality in very large scale integrated computer-aided design flow. The objective of the delay-budgeting problem investigated in this paper is to maximize the total delay budget assigned to each node in a directed acyclic graph under a given timing constraint. Due to the discreteness of the timing of the components in the libraries during design-optimization flow, discrete solution for delay budgeting is essential. We present an optimal integer delay-budgeting algorithm. We prove that the problem can be solved optimally in polynomial time. In addition, we look at different extensions of the delay-budgeting problem, such as maximization of weighted summation of delay budgets assigned to the nodes with constraints on the lower and upper bounds on the delay budget allocated to each node. We prove that for both aforementioned extensions, our algorithm can produce an optimal integer solution in polynomial time. Our algorithm is generic and can be applied at different design tasks at different levels of abstraction. We applied our proposed optimal delay-budgeting algorithm in library mapping during datapath synthesis on a field programmable gate array (FPGA) platform, using preoptimized cores of FPGA libraries. For each application, we go through synthesis and place and route stages in order to obtain accurate results. Our optimal algorithm outperforms the zero-slack algorithm (Nair et al. 1989) in terms of area by 10% on average for all applications. In some applications, optimal delay budgeting can speedup runtime of place and route up to two times.

Buffer delay change in the presence of power and ground noise

Variations of power and ground levels affect very large scale integration circuit performance. Trends in device technology and in packaging have necessitated a revision in conventional delay models. In particular, simple scalable models are needed to predict delays in the presence of uncorrelated power and ground noise. In this paper, we analyze the effect of such noise-on-signal propagation through a buffer and present simple, closed-form formulas to estimate the corresponding change of delay. The model captures both positive (slowdown) and negative (speedup) delay changes. It is consistent with short-channel MOSFET behavior, including carrier velocity saturation effects. An application shows that repeater chains using buffers instead of inherently faster inverters tend to have superior supply-level-induced jitter characteristics. The expressions can be used in any existing circuit performance optimization design flow or can be combined into any delay calculations as a correction factor.

Cost‐based approach for sizing of pedestrian facilities

AbstractPedestrian facility size is currently determined in direct relationship to the design level of service. However, the design level of service is chosen arbitrarily from the six levels of service, which are assumed to represent the freedom available for movement at different levels of pedestrian flow. This direct and simple approach to facility sizing is shown to have two fundamental deficiencies that contribute to wasteful over capacity. In this article, a cost‐based approach is introduced to overcome the deficiencies. Two analytical models, one for determining optimal design density and another for determining optimal design flow, are presented. The optimum design parameters minimize the total cost of the facility defined as the sum of construction cost and user cost. The sensitivity of the optimum parameters to the cost and pedestrian flow parameters is demonstrated using a numerical example.