Optical Proximity Effect Correction Research Articles

Improvement of YX42° Cut LiTaO3 SAW Filters with Optical Proximity Effect Correction Method.

Due to the influence of the optical proximity effect (OPE), it is easy for a pattern of photoresistance to be inconsistent with a design pattern, thus damaging the performance of a SAW resonator. To solve this problem, this paper proposes an optimization method for SAW filters based on optical proximity correction (OPC). This method can avoid the tip discharge problem of SAW filters by suppressing the problem of rounding and shrinking of dummy electrode and electrode tail caused by OPE. This method increases the quality factor (Q) of the SAW resonator and thus decreases the insertion loss of the SAW filter. The filter increases the bandwidth by 1.8 MHz at -1.5 dB after applying the OPC method. Additionally, it improves the stability of the filter under high power conditions.

Improvement of optical proximity-effect correction model accuracy by hybrid optical proximity-effect correction modeling and shrink correction technique for 10-nm node process

The model accuracy of optical proximity-effect correction (OPC) was investigated by two modeling methods for a 10-nm node process. The first method is to use contours of two-dimensional structures extracted from critical dimension-scanning electron microscope (CD-SEM) images combined with conventional CDs of one-dimensional structures. The accuracy of this hybrid OPC model was compared with that of a conventional OPC model, which was created with only CD data, in terms of root-mean-square (RMS) error for metal and contact layers of 10-nm node logic devices. Results showed improvement of model accuracy with the use of hybrid OPC modeling by 23% for contact layer and 18% for metal layer, respectively. The second method is to apply a correction technique for resist shrinkage caused by CD-SEM measurement to extracted contours for improving OPC model accuracy. The accuracy of OPC model with shrink correction was compared with that without shrink correction, and total RMS error was decreased by 12% by using the shrink correction technique. It can be concluded that the use of CD-SEM contours and the shrink correction of contours are effective to improve the accuracy of OPC model for the 10-nm node process.

Design intent application to tolerance-based manufacturing system

Continuous shrinkage of the design rule in large-scale integrated circuit devices brings about greater difficulty in the manufacturing process. The keys to meeting small process margin are adequate extraction of critical dimension tolerance for each object, considering design intent in terms of electrical behavior, and assigning the tolerance for each process step. However, once the design data are converted to layout data and signed off, most of the design intent is abandoned and unrecognized in the process phase. Thus, uniform and redundant tolerance is used, and therefore, excess tolerance is assigned for some layouts. To solve the problem described above, a tolerance-based manufacturing system utilizing flexible layout-dependent speculation derived from design intent has been discussed. Using a 40-nm node test chip, electrically critical spots, such as timing, cross-talk noise, electromigration, with small margins are extracted, assigned to the physical layout, and utilized in the manufacturing process. The flow is applicable for optical proximity effect correction (OPC) turnaround time reduction, optimization of OPC/lithography compliance check (LCC) specification, and failure-analysis acceleration. Consequently, a design-intent-aware manufacturing system is promising for realizing proper process specifications and computational cost reduction, in addition to yield enhancement.

Restricted Optical Proximity Effect Correction Pattern Generation Based on Optical Proximity Effect Correction-Design for Manufacturability Rule in Model-Based Optical Proximity Effect Correction: Application for Metal Layer in Complementary Metal–Oxide–Semiconductor Logic Process

In the recent submicron technologies, the pattern formation on photomasks is increasing in its difficulty owing to the complexity of optical proximity effect correction (OPC) and resolution enhancement techniques (RET). The detection and repair of critical patterns after OPC or RET have become essential procedures for photomask preparation, and design rule check (DRC) or lithography simulation tools have often been used to verify these patterns. However, the detection and repair of critical patterns have been becoming an excessive burden in the development of lithography processes and mask data processing. In this paper, we describe how to detect and repair these OPC critical patterns in lithography using the OPC-DFM rule, which can be derived from the OPC extraction test element group (TEG) effectively and easily. This technology enables the removal of OPC critical patterns before photomask preparation.

Automated hot-spot fixing system applied to the metal layers of <inline-formula><math altimg="none" display="inline" overflow="scroll"><mrow><mn>65</mn><mtext>-</mtext><mi>nm</mi></mrow></math></inline-formula> logic devices

Hot-spot clearance using process simulation is indispensable for low-k1 lithography processes. Hot spots will occur mainly depending on local pattern context. Appropriate calibration of design rules, mask data preparation, resolution enhancement techniques, and optical proximity effect correction will reduce potential hot spots. However, pattern layout variety is so enormous that, even with the most careful calibration of every process, an unexpected potential hot spot is occasionally left in the design layout. Manual modification of the design at the hot spot will be effective, but it takes too much time. Therefore, there is a need for an automated hot-spot fixing system so as to avoid fatal hot-spot occurrence, with sufficient process margins and short turnaround time. We developed an automated hot-spot fixing system, the hot-spot fixer (HSF). Design data is automatically modified according to the instruction at every hot spot, complying with the design rule. We applied the HSF system to the metal layer of logic devices of 65 nm and most of the hot spots were diminished throughout a full chip within 12 hours. Thus, HSF feasibility has been proved for metal layers in the 65-nm node and below with full-chip data volume.

Mask Cost and Profitability in Photomask Manufacturing: An Empirical Analysis

An empirical study of the economics of manufacturing photomasks concludes that the uncontrolled growth of optical proximity effect correction and resolution enhancement techniques is driving up the cost of pattern generation and mask inspection to levels that threaten the profitability of photomask manufacturing. The intrinsic cost of some leading edge photomasks has already exceeded the price that customers are willing to pay for them. A model of the lifecycle of photomask manufacturing, developed from interviews involving the 1990-to-2005 operations of six mask shops and a survey of seven photomask manufacturers, shows that design for manufacturability (DFM) constitutes the most promising approach for alleviating this market impasse. Unilateral action by mask shops to increase their capital productivity is necessary but insufficient and perhaps unaffordable. DFM solutions will require the majority of participants in the lithography value chain to collaborate according to a volatile demand schedule that is driven by semiconductor manufacturers

Maskless Fabrication of Highly-Ordered Periodic Nanopillars using FIB and Bitmap Control

Nanopillars have many potential applications, e.g., in making biochips for DNA separation, fast genome sequencing analysis and producing photonic crystals. The form of lithography used in the semiconductor industry, optical projection lithography (OPL), can be used to produce feature sizes below 100 nm. However, a pattern must be first created on a mask, a large and heavy (over 1000 kg) and very expensive reduction lens has to be used to project the image of the mask onto a Si wafer, and high quality photoresist is needed to record the projected image. To achieve nanoscale precision, a variety of resolution-enhancement techniques have to be employed, including phase-shift masks, off-axis illumination, and optical proximity-effect correction. The cost of a set of masks for producing a chip can be well over US$2 million. The difficulty, time, and prohibitively high cost associated with designing and repairing a mask makes OPL unsuitable for exploring innovative applications of nanostructures. We demonstrate that FIB can be controlled effectively using bitmap to provide a one-step maskless nanofabrication tool for making microand nanoscale pillars (Figs. 1-2). In principle, the technique can be extended to make other nanostructures such as nano-gratings and nano-wells for various useful applications.

Mask Pattern Correction by Energy Loss Compensation in Extreme Ultraviolet Lithography

In extreme ultraviolet (EUV) lithography with off-axis incidence, the incident light loses energy when it is reflected from a mask onto a wafer because the absorber pattern blocks some of the incident and diffracted light, and the absorber side wall reflects some of the incident light. This study concerns mask pattern correction to compensate for the energy loss at the pupil. Simple negative biasing was found to be an effective compensation technique. That is, when the absorber stack is thin, a narrowed mask pattern by adding a negative bias and off-axis incidence produce about the same optical proximity effects (OPE) as an unbiased mask and normal incidence. This makes it possible to use conventional algorithms for optical proximity effect correction (OPC), which are optimized for normal incidence. For a thin absorber stack, combining energy loss compensation for off-axis incidence with conventional OPC for normal incidence provides excellent pattern fidelity, sufficient critical dimension (CD) uniformity, and good pattern edge contrast at the same time.

Monte Carlo Simulation Study of Local Critical Dimension Error on Mask and Wafer

Sub-100 nm lithography has been realized recently in the IC industry. The resolution enhancement techniques (RET) and optical proximity effect correction (OPC) require more complicated mask patterns. It is therefore, very important to simulate and calculate mask error enhanced factor (MEEF), and critical dimension (CD) variations on the mask and wafer correctly using optical simulation tool before manufacturing. However, the expectations of MEEF and CD error using the in-house optical simulation tool, Topo, are larger than those of the experimental result. These are caused by many reasons. The ignorance of the vector property of light could be one reason. In case of using higher numerical aperture (NA), the vector property of light, such as polarization, should be taken into account when calculation of printed image on wafer. Also, the ignorance of the local CD error caused by the neighborhood could be another reason. The second issue described above has been studied using the Monte Carlo (MC) method, a commonly used statistical method. We assume that all of the factors follow the normal curve with a certain standard deviation. This assumption is sufficient for studying local CD error by the MC method. When the local CD variation on the mask for the design rule 110 nm is 3 nm in its 3σ, CD variation of approximately 2.0 nm on wafer is expected by the MC method. This result is fairly comparable with experimental one, when the MEEF is about 2.7 locally. We obtain another MEEF value, around 4.1 globally, when the mask CD deviates from the target CD by ±12 nm in 3σ. This study shows that the MC method gives a result close to that of the experimental one greater than 2.5 of MEEF locally.

Monte-Carlo-Based Automatic Design of Chromeless Phase Shift Mask

The optical proximity effect correction algorithm (OPERA) program based on the Monte-Carlo method has been used for optical proximity correction (OPC) and phase shift mask (PSM) generation for low-NA projection lithography systems. To apply OPERA to high-NA systems, we adopted an imaging model based on a vector diffraction theory. Also, we developed a new convergence algorithm that does not reduce the degree of freedom and prevents the convergence process from falling into a local minimum. The new program, OPERA-V, is at least 10 times faster than the previous version. OPERA-V not only improves the computation time of traditional OPC, but can also be used as an automatic design tool for creating chromeless PSMs.

Pattern printability for off-axis incident light in extreme ultraviolet lithography

Off-axis incident light produces shadowing and an imbalance in the diffracted light. Shadowing causes a change in the critical dimension (CD) and a shift in the position of patterns due to the multiple interference of the absorber and buffer layers. In addition, the imbalance in the diffracted light influences the optical proximity-effect correction (OPC) of actual patterns with a process factor k1 below 0.6. In this study, the main factors influencing OPC were investigated. These include asymmetric aberrations and optical proximity effects (OPE) in line patterns. OPC was then applied to a T-shaped pattern. It is found that the mask error factor (MEF) in low-contrast regions of a layout is an important consideration in OPC.

A 0.11 μm CMOS technology featuring copper and very low k interconnects with high performance and reliability

This paper describes a 0.11 μm CMOS technology with high-reliable copper (Cu) and very low k (VLK) ( k<2.7) interconnects for high-performance and low-power applications of a 0.13 μm generation. Aggressive design rules, 0.11 μm gate transistor and 2.2 μm 2 six-transistor SRAM cell are realized by using KrF 248 nm lithography, optical proximity effect correction, and gate-shrink techniques. Eight-level interconnects are fabricated with seven level of Cu/VLK interconnect and one level of Al/SiO 2 interconnect. Drain current of 0.67 and 0.28 mA/μm are realized for nMOSFET and pMOSFET with 0.11 μm gate, respectively. Propagation delay of two input NAND with the Cu/VLK interconnect is estimated. The delay is improved by more than 70%, compared to 0.18 μm CMOS technology with Cu/FSG interconnects. Functional 288 kbit SRAM circuit is demonstrated with 2.2 μm 2 cell and Cu/VLK interconnect.

Optimization method of the double exposure technique with alt-PSMs for below a 0.13 μm node

A new method to optimize the structure of alternative phase shifting masks (alt-PSMs) with dual trench type and optical proximity effect correction (OPC) has been developed from the viewpoint of pattern placement error and gate width fluctuation. The pattern placement error and gate width fluctuation have been reduced significantly to meet the requirements of overlay margin and critical dimension (CD) accuracy for the 0.13 μm node devices by this method. The optimum mask structure for reducing a pattern placement error was determined by the simulation that takes account of the mask topography effect. The alt-PSM with a deep trench depth of 570 nm and a phase difference of about 170° between the phase shifted and nonshifted area was optimum to reduce pattern placement error. At the optimum condition, a high contrast was also obtained. For the experiment, we used a set of masks to study dependence of mask cross sectional structure. While the dependence of pattern placement error on focus shift is much larger for the nonoptimized mask, it is small with the mask having the optimized value of our study. With respect to the gate width fluctuation, it can be categorized into three folds. We have developed optimization methods for them, respectively. First one is associated with pattern pitches and shifter lengths. It could be reduced by mask bias OPC of a binary mask. Second one is gate width fluctuation at the end of shifter. Third one is what we call necking shape, which is pattern shrinkage near the end of shifter. For the latter two cases, we have applied OPC of extended shifters with additional patterns. Linewidth fluctuation was reduced by applying these OPC to the pattern.

A Study of Loading Effect during Electron-Beam Exposure and Etching Process in Photomask Fabrication

As the requirements of critical dimension (CD) uniformity on photomasks continue to tighten with advanced logic and memory devices, the dry etching process should be adopted to meet the needs of the optical proximity effect correction (OPC) and reduced bias process [W. T. Chen and M. Kamma: Proc. SPIE 3412 (1998) 149.]. There are severe CD variations in the dry etching process due to chrome (Cr) pattern density with various clear and dark fields. Through experiments, on the CD variation was investigated in the wet etching process, as well as in the dry etching process. This work focused on the tracing-determining the actual cause of the loading effect. It was revealed that what accounts for a major portion of the loading effect is not the Cr dry etching process, but the rescattering of electrons of the electron-beam exposure system. Rescattered electrons in this article refers to electrons that are reflected between the specimen and the lower parts of the electron-beam column and expose the unexposed area. In this paper, the existence of rescattered electrons was experimentally confirmed with a 10 kV acceleration-voltage system and the CD variation by reflected electrons was also investigated.

Lithography Computer Aided Design Technology for Embedded Memory in Logic

We have developed an optical proximity effect correction (OPC) flow for both, the repetitive memory cell patterns by a simulation-based method and for the random logic application specific IC (ASIC) patterns by a rule-based method. Application results for a 0.28 µm static random access memory (SRAM) cell and 0.25 µm ASIC devices have shown that correction time and final data size were feasible for conventional layout design flow and mask fabrication. Also, our system has achieved significant improvement with respect to pattern printing fidelity between designed and printed resist patterns. In addition to this, an automatic alternative phase shift mask (PSM) pattern layout tool has been developed. Using the tool with a double exposure method, 0.16 µm gate patterns for both logic and dynamic random access memory (DRAM) have been obtained with a positive photoresist. The developed lithography computer aided design (CAD) technology has improved the accuracy of pattern formation for state of the art device fabrication. The fabricated patterns have satisfied the required linewidth accuracy, within ±10% of the design value, ones under the practical exposure-focus window.

Simulation-Based Automatic Optical Proximity Effect Correction Adaptive for Device Fabrication

A new optical proximity effect correction (OPC) method adaptive for device fabrication has been developed, focusing on the evaluation method of printed images through simulation. The evaluation procedure of this method is consist of not only measurement of edge placement error of the printed image but analysis of the shape of the printed image. Automatic correction which is flexible for various pattern shapes is available, and distortion via overcorrection is prevented. By using this method for 0.28 µ m static random access memory (SRAM) poly-Si patterns, an excellent distortion-free printed image adequate for actual device fabrication processing has been obtained with simple mask patterns. The SRAM cell size was reduced to as small as 5 µ m2.

Practical Optical Proximity Effect Correction Adopting Process Latitude Consideration

For an optical lithography process with a design rule of under 0.35 µ m, printed resist pattern size and shape tend to differ from those designed because of the optical proximity effect, resulting in line width error and corner rounding. In order to solve such problems, a new optical proximity effect correction (OPC) system taking account of the resist development and process latitude has been developed. The system is designed focussing on accurate optimization of cell patterns such as memory or gate array devices. Using this OPC for a memory device cell pattern of 3.5×6.3 µ m area, the resist edge placement error with process conditions of within ±5% exposure latitude and ±0.75 µ m depth of focus achieved was one-third of that without OPC. The calculation time for this correction is as short as 2 minutes on a 135 MIPS workstation even with the resist development and process latitude consideration.

Role of etch pattern fidelity in the printing of optical proximity corrected photomasks

Optical proximity effect correction has been proven to improve critical dimension control, increase overlay margins, and, when used with phase-shifting masks and/or modified illumination and mask-plane nonprinting assist features, also extend resolution and increase depth of focus of current generation lithographic exposure technology. While the potential enhancements afforded by such schemes are enticing, their successful implementation is imposing demands on mask fabrication, inspection, and repair which surpass the state of the art in industry today. This article focuses on the influence of the mask pattern fidelity on the ensuing wafer lithographic performance. Both wet and dry etch techniques were applied to an ensemble of proximity-corrected test patterns using standard binary chrome-on-glass test masks. The chrome was wet etched with polybutene sulfone as the masking resist using an optimized zero-bias process. For comparison, the same test structures delineated with a silicon containing resist were also reactive ion etched with Cl2/O2/N2 chemistry, developed to retain submicron pattern fidelity, and anisotropic absorber wall profile. Comparative wet and dry-etched mask and resulting wafer metrology results are presented for 5× i-line and 4× deep ultraviolet exposures.