Abstract
For an optical lithography process with a design rule of under 0.35 µ m, printed resist pattern size and shape tend to differ from those designed because of the optical proximity effect, resulting in line width error and corner rounding. In order to solve such problems, a new optical proximity effect correction (OPC) system taking account of the resist development and process latitude has been developed. The system is designed focussing on accurate optimization of cell patterns such as memory or gate array devices. Using this OPC for a memory device cell pattern of 3.5×6.3 µ m area, the resist edge placement error with process conditions of within ±5% exposure latitude and ±0.75 µ m depth of focus achieved was one-third of that without OPC. The calculation time for this correction is as short as 2 minutes on a 135 MIPS workstation even with the resist development and process latitude consideration.
Published Version
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