New method for reducing across chip poly-CD variation with statistical OPC/gauge capability analysis

Abstract

For a lithography process with a design rule of 0.18 micrometers and beyond, the most critical issue is the gate critical dimension (CD) control because it affects the circuit performance especially for high-end logic devices directly. The gate CD variation is generally categorized into two folds. The first one is CD variation affected by optical and process proximity effects, which is pattern layout dependent errors and can be treated by automatic optical proximity effect correction (OPC). The second one is across chip line width variation (ACLV) caused by aberration of stepper/scanner exposure tools and mask writing error. Although both two have been studied in detail respectively, the composite errors are not studied sufficiently. This is because these errors can not necessarily be quantified for all the pattern layout configuration exists in the actual device chips. In this paper we will propose a new analysis method to quantify OPC performance and gauge capability of in-process quality control (IPQC) monitors. The method consists of two parts. The first is to verify validity of OPC by using IPQC monitor patterns and the second is to quantify gauge capability of the IPQC monitor patterns for representing ACLV. Our new analysis method is significantly effective and persuasive for verifying OPC performance as well as gauge capability of IPQC monitor patterns. It is also quite useful to optimize OPC parameters and methods to reduce ACLV that is most critical to obtain high-end logic devices with a design rule of 0.15 um and below.