Optical Interconnect Architecture Research Articles

Power Efficiency Comparisons of Interchip Optical Interconnect Architectures

High-bandwidth interchip optical interconnect architectures have the potential to address increasing input-output bandwidth demands. This brief compares several optical interconnect architectures on the basis of power efficiency in 90- and 45-nm CMOS technologies. Under consideration are a near-term architecture consisting of discrete vertical-cavity surface-emitting lasers (VCSELs) with p-i-n photodetectors (PDs) and three long-term integrated photonic architectures that use waveguide metal-semiconductor-metal PDs and either electroabsorption modulator (EAM), ring resonator modulator (RRM), or Mach-Zehnder modulator (MZM) sources. An optimal current density methodology with normalized transistor parameters extracted from circuit simulations is applied to jointly optimize driver and receiver circuitry to minimize the total link power dissipation. The analysis results show that the VCSEL-based link is limited by VCSEL bandwidth and maximum power levels, rather than circuit bandwidth, and achieves a maximum of 24 Gb/s in both the 90- and 45-nm nodes. The EAM and the RRM are both attractive integrated photonic technologies capable of scaling data rates past 30 Gb/s at power efficiency levels near 0.5 mW/Gb/s in the 45-nm node and are primarily limited by coupling and device insertion losses. While the MZM offers robust operation due to its wide optical bandwidth, significant improvements in power efficiency must be achieved to become applicable for high-density applications.

Two-step scheduling framework for space-wavelength modular optical interconnection networks

Current interconnection architectures based on electronics are approaching their physical limitations especially in terms of interconnection wiring and power density. To overcome these issues, the flexibility and the scalability of optical technologies can be exploited. This paper considers a modular optical interconnection architecture that consists of multiple cards, supporting a fixed number of ports and interconnected through a passive optical backplane. A two-step scheduling framework (TSS) is proposed, which exploits the modularity of the architecture and the existing scheduling algorithms, while satisfying the peculiar scheduling constraints of the architecture. In TSS, an intra-card step decides the wavelength switching configuration and then an inter-card step decides the space switching configuration. Each step can be run in parallel, on the cards and on the wavelengths, respectively. TSS is compared against a single-step scheduler suitable for non-modular architectures, under different traffic patterns and architecture configurations. TSS performs better in terms of lower packet delay, higher throughput and lower computational complexity. Finally, the possibility of increasing the packet transfer rate (transfer speedup) can be included in TSS without additional complexity and is especially beneficial for the bursty and skewed traffic patterns, typically experienced in real scenarios.

A novel reconfigurable optical interconnect architecture using an Opto-VLSI processor and a 4-f imaging system

A novel reconfigurable optical interconnect architecture for on-board high-speed data transmission is proposed and experimentally demonstrated. The interconnect architecture is based on the use of an Opto-VLSI processor in conjunction with a 4-f imaging system to achieve reconfigurable chip-to-chip or board-to-board data communications. By reconfiguring the phase hologram of an Opto-VLSI processor, optical data generated by a vertical Cavity Surface Emitting Laser (VCSEL) associated to a chip (or a board) is arbitrarily steered to the photodetector associated to another chip (or another board). Experimental results show that the optical interconnect losses range from 5.8dB to 9.6dB, and that the maximum crosstalk level is below -36dB. The proposed architecture is tested for high-speed data transmission, and measured eye diagrams display good eye opening for data rate of up to 10Gb/s.

Can Simple Optical Switching Fabrics Scale to Terabit per Second Switch Capacities?

The design of fabrics for terabit packet switches and routers needs to consider the limitations imposed by electronic technologies. In particular, attention has to be paid to information density and to power consumption and dissipation, as well as to power supply and footprint requirements. Optical technologies can overcome some of these limitations. We analyze the use of optical fabrics to interconnect line cards in terabit packet switches and routers. For this purpose, single-plane and multiplane optical interconnection architectures are proposed that exploit wavelength agility at line cards to implement the required switching functionality. The physical-layer scalability and feasibility of these architectures are studied by using realistic models, mostly based on the characteristics of commercially available optoelectronic devices. As a result, the considered architectures can be characterized in terms of power budget and signal-to-noise ratio, enabling the computation of the maximum achievable port count and aggregate switching capacity. Our results show that aggregate capacities of the order of a few terabits per second are possible in very simple optical switching fabrics and that the multiplane architectures permit a complexity trade-off between the wavelength and space domains, making the overall design more feasible.

Phastlane

Tens and eventually hundreds of processing cores are projected to be integrated onto future microprocessors, making the global interconnect a key component to achieving scalable chip performance within a given power envelope. While CMOS-compatible nanophotonics has emerged as a leading candidate for replacing global wires beyond the 22nm timeframe, on-chip optical interconnect architectures proposed thus far are either limited in scalability or are dependent on comparatively slow electrical control networks. In this paper, we present Phastlane, a hybrid electrical/optical routing network for future large scale, cache coherent multicore microprocessors. The heart of the Phastlane network is a low-latency optical crossbar that uses simple predecoded source routing to transmit cache-line-sized packets several hops in a single clock cycle under contentionless conditions. When contention exists, the router makes use of electrical buffers and, if necessary, a high speed drop signaling network. Overall, Phastlane achieve 2X better network performance than a state-of-the-art electrical baseline while consuming 80% less network power.

Fault Tolerance Routing for Wavelength Routed Optical Networks in ONoC

As a promising replacement for the conventional wire-connected on-chip micro-networks, the wavelength routed optical network (WRON) is an optical interconnection architecture particularly suitable for future super large system-on-chips. In this paper, we will lay down the theoretical foundations concerning the enumeration of all the routing paths that exist in a WRON. Actually, all the links and the nodes that a routing path has to pass through can now be enumerated under this proposed theoretical framework. Availability of such detailed information of a routing path at the node/link level makes it possible to analyse the WRON network behaviour when a fault exists. Specially, four types of faults are modelled in the WRON, and subsequently, we propose a set of procedures to locate the fault if it exists. Because the data transmission in an optical network is at the speed of light, the delay due to the non-shortest path data transmission tends to be negligibly small. This observation leads us to propose a multiplepass-transmission (MT) scheme which can be applied to rebuild the data transmission paths by bypassing/avoiding the detected fault location.

Changing the colour of light in a silicon resonator

As the demand for high bandwidths in microelectronic systems increases, optical interconnect architectures are now being considered that involve schemes commonly used in telecommunications, such as wavelength-division multiplexing (WDM) and wavelength conversion1. In such on-chip architectures, the ability to perform wavelength conversion is required. So far wavelength conversion on a silicon chip has only been demonstrated using schemes that are fundamentally all-optical2,3,4,5,6, making their integration on a microelectronic chip challenging. In contrast, we show wavelength conversion obtained by inducing ultrafast electro–optic tuning of a microcavity. It is well known that tuning the parameters of an optical cavity induces filtering of different colours of light7. Here we demonstrate that it can also change the colour of light. This is an effect often observed in other disciplines, for example, in acoustics, where the sound generated by a resonating guitar string can be modified by changing the length of the strings (that is, the resonators)8. Here we show this same tuning effect in optics, enabling compact on-chip electrical wavelength conversion. We demonstrate a change in wavelength of up to 2.5 nm with up to 34% on–off conversion efficiency.

System simulation methodology of optical interconnects for high-performance computing systems

The relentless quest for processing speed in the range of teraflops and beyond has accelerated the need for scalable, parallel, high-performance computing (HPC) systems. To meet this high bandwidth and low power requirements, optical interconnect-based system architectures are being implemented by the HPC industry. While computer-aided design tools have significantly assisted electronic system simulation, the field of system level optoelectronics modeling has lagged behind owing to lack of simulation methodologies and tools. This paper explores the design space of developing OPTISIM, a system level modeling and simulation methodology of optical interconnects for HPC systems. OPTISIM can provide computer architects, designers, and researchers a highly optimized, efficient, and accurate discrete-event environment to test various research hypotheses on HPC systems with power-performance implications. For any given optical interconnect architecture with optical transceivers, wavelength assignment, and traffic patterns, OPTISIM provides end users with network throughput, average latency, power loss, power consumption, and signal strength at the output. The proposed OPTISIM simulation methodology is explained with a case study on the performance of an optical HPC architecture called RAPID.

Wavelength-division-multiplexing optical Benes-type networks with simultaneous space-wavelength switching

We propose new wavelength-division-multiplexing (WDM) optical interconnect architectures with simultaneous space-wavelength switching capability and reduced complexity. The proposed architectures improve over existing space-wavelength Benes networks, as these require the same number of stages and hardware components as a pure space Benes network. In addition, wavelength conversion in the proposed designs occurs only between two predefined wavelengths, eliminating the need for expensive wide-range wavelength converters used in most existing designs. We develop and characterize three families of WDM Benes networks with reduced complexity, and we present a typical architecture in each of the families. We also propose a routing strategy to establish connections over each of the proposed families. Finally, we present a comparative analysis of the properties of proposed architectures with respect to known WDM Benes networks. It is shown that the new designs require a smaller number of switching stages and space switches, and they have a smaller overall cost compared to most existing WDM Benes interconnects.

High-speed (2.5 Gbps) reconfigurable inter-chip optical interconnects using opto-VLSI processors

Reconfigurablele optical interconnects enable flexible and high-performance communication in multi-chip architectures to be arbitrarily adapted, leading to efficient parallel signal processing. The use of Opto-VLSI processors as beam steerers and multicasters for reconfigurable inter-chip optical interconnection is discussed. We demonstrate, as proof-of-concept, 2.5 Gbps reconfigurable optical interconnects between an 850nm vertical cavity surface emitting lasers (VCSEL) array and a photodiode (PD) array integrated onto a PCB by driving two Opto-VLSI processors with steering and multicasting digital phase holograms. The architecture is experimentally demonstrated through three scenarios showing its flexibility to perform single, multicasting, and parallel reconfigurable optical interconnects. To our knowledge, this is the first reported high-speed reconfigurable N-to-N optical interconnects architecture, which will have a significant impact on the flexibility and efficiency of large shared-memory multiprocessor machines.

Fast Electrooptic Bragg Grating Couplers for On-Chip Reconfigurable Optical Waveguide Interconnects

We present an array of electrooptic Bragg gratings for on-chip optical waveguide interconnect applications. These integrated gratings can serve as switchable couplers to couple high-speed optical signals from a vertical-cavity surface-emitting laser to on-chip polymeric waveguides and from waveguides to photodetectors. The unique switching feature provides a promising solution to facilitate dynamically reconfigurable on-chip optical interconnects architecture for intrachip, chip-to-chip, and board-to-board data communications. We demonstrate electrooptic grating couplers in a polymeric channel waveguides on a silicon substrate with an electrically tunable surface-normal coupling efficiency up to 8% and a switching speed of 75 μs.

Low-stress hybridisation of emitters, detectors and driver circuitry on a silicon motherboard for optoelectronic interconnect architecture

In the absence of a truly integrated silicon optoelectronics technology, manufacturable hybridisation technologies for III–V optoelectronic components, compatible with silicon and CMOS substrates, are essential for optoelectronic interconnect. The hybridisation technology for a clock distribution optical interconnect architecture is reported. A substrate removal technology for an 8×8 array of 10 μm thick VCSEL coupons is described, and the performance of AlAs and AlGaAs etch stop layers is discussed. Optoelectronic systems which depend on the retention of the polarisation specific nature of components restrict the mechanical constraints on their manipulation and bonding, to avoid stresses which could destroy the polarisation specificity of the component. A low-stress pick and place technology using a mask aligner has been employed. Eight hundred and fifty nanometres top-surface emitting GaAs/AlGaAs VCSELs, InGaAs/InP p–i–n photodiode arrays, and high-frequency CMOS silicon driver chips have been hybridised on silicon motherboards using this technology. The factors influencing the choice of bonding materials and the sequence of component hybridisation, including the requirements of subsequent planarisation and wiring processes, are discussed. The sources of alignment error are reported. Examples of working emitters, detectors and driver circuitry hybridised using this technology are presented.

Epitaxy-on-Electronics technology for monolithic optoelectronic integration: foundations, development, and status

Joseph F. AhadianClifton G. Fonstad, Jr.Massachusetts Institute of TechnologyDepartment of Electrical Engineeringand Computer Science77 Massachusetts AvenueRoom 13-3030Cambridge, Massachusetts 02139E-mail: joeah@oevlsi.mit.eduAbstract. Optoelectronic very large scale integrated (OE-VLSI) circuitsare a basic component of optical interconnects proposed to overcomethe limitations of high-speed electrical interconnects. Epitaxy-on-electronics (EoE), a monolithic integration technology capable of com-bining thousands of optoelectronic devices with VLSI-complexity GaAsElectronics, is reviewed. The fundamental assumptions on which theEoE technology is founded are explained and the development of theEoE integration process is reviewed. Then, the recently completedOPTOCHIP research foundry project, which made LED-based optoelec-tronic integrated circuits (OEICs) available to optical interconnect re-searchers, is described. Finally, integrated LED, photodetector, and cir-cuit characterization results are detailed. These results show the utility ofEoE OEICs in implementing optical interconnect architectures and pointout current performance limitations.

Fundamental limits on bandwidth, efficiency, and parallelism in all-optical and hybrid fan-in

We present an investigation of relationships among the information bandwidth, the optical power efficiency, and the degree of parallelism for optical interconnection architectures that employ optical fan-in. The foundation for these relationships is the Lagrange invariant, or, more specifically, the constant-radiance theorem. We show that, when restrictions imposed by the constant-radiance theorem are combined with requirements on the probability of error, an upper limit is placed on the bandwidth that is reduced as the fan-in ratio increases. These limitations are significantly more severe when optical fan-in is used to perform analog summations. We then define a measure of processing efficiency that takes into account the influence of optical input power on the probability of error and is used to interpret the results.

Intraplane to interplane optical interconnects with a high diffraction efficiency electro-optic grating

We report on a new optical interconnect architecture for three-dimensional, multiple electro-optic gratings with LiNbO(3) used in conjunction with substrate guided waves. First the operating mechanism of the system is studied in detail, and the momentum mismatch in the operating process of the system is also demonstrated. We then derive a new method for calculating coupling efficiency by introducing a compensation for the mismatch. This theoretical research allows the new optical interconnect architecture to provide a higher design accuracy and an optimized coupling efficiency, even though it is under the case of momentum mismatch. We achieve this result by introducing a substrate guided wave with 45 degrees bouncing angle and 100-V applied voltage. The successful design and its theoretical analysis will be helpful for research on the grating coupler.

Segmented Fresnel zone lens elements with several primary foci

The use of holographic elements containing segmented Fresnel zone lenses to generate more than one primary focus is investigated. Elements are designed to provide tolerance to misalignment in free space optical interconnection architectures where this is a key consideration. The kinoform profile is approximated in multi-level form in quartz glass using micro-structuring technologies. Elements are of 2 mm diameter, f 5 performance and intended for use at 1.52 μm wavelength. To optimise their efficiency they are provided with anti-reflection coatings by ion beam sputter deposition. Diffraction efficiencies are 70% for 8-level structures divided between two focal spots, and 36% for 2-level structures generating four foci. The measured spot diameter is 21 μm between first minima. Tolerance to misalignment is demonstrated.

Time multiplexing and control for optical cellular-hypercube arrays

We discuss the cellular-hypercube optical free-space interconnection architecture and its implementation by two-dimensional smart-pixel optoelectronic cellular arrays. We emphasize the behavior of the cellular hypercube in performing shift-invariant parallel shifts of data, a basic requirement of most single-instruction multiple-data algorithms. We present a time-multiplexing scheme for realizing the cellular hypercube, showing that the communication time is inversely proportional to the number of optical detectors per cell. We also present an improved hybrid interconnection network with improved performance that combines the cellular hypercube and mesh, using optics for the longer-distance connections and electronics for nearest-neighbor connections.

Design and simulation of PLZT-based scanning grating lobe optical array generators

The unique properties of quadratic lead lanthanum zirconate titanate (PLZT) compositions make feasible the development of scanning grating lobe optical array generators. Scanning optical array generators would facilitate the alignment of optical interconnect architectures and could provide a critical technology for the implementation of parallel addressing schemes in threedimensional optical memories. A three-port implementation of a PLZT-based scanning optical array generator is presented. The three-port implementation offers a significant reduction in the maximum electrode voltage required to effect a specific scan angle.

Monolithic optical switching technology for a programmable optical logic gate array

Monolithic optical switches based on the integration of GaAs/AlGaAs vertical-cavity surface-emitting lasers with heterojunction phototransistors and photothyristors have evolved from a family of simple switches and logic capabilities to more complex switch nodes with increased functionality that are capable of performing optical logic and routeing in a dynamically programmable manner. The operation of these switches in different routeing and logic configurations is experimentally demonstrated. This technology provides the basis for compact, programmable optical logic processing and interconnection architectures, including a dynamically reconfigurable optical logic gate array that can be programmed using stored instruction sets (control voltages) to perform different combinational optical logic functions.

Comparison between optical interconnection processors: folded perfect-shuffle versus three-dimensional butterfly

The differences between folded perfect shuffle and three-dimensional (3-D) multi-channel butterfly optical interconnection architectures are quantified. The three-dimensional butterfly network, in particular, is used to implement Hartley transform operation.