Low-stress hybridisation of emitters, detectors and driver circuitry on a silicon motherboard for optoelectronic interconnect architecture

Abstract

In the absence of a truly integrated silicon optoelectronics technology, manufacturable hybridisation technologies for III–V optoelectronic components, compatible with silicon and CMOS substrates, are essential for optoelectronic interconnect. The hybridisation technology for a clock distribution optical interconnect architecture is reported. A substrate removal technology for an 8×8 array of 10 μm thick VCSEL coupons is described, and the performance of AlAs and AlGaAs etch stop layers is discussed. Optoelectronic systems which depend on the retention of the polarisation specific nature of components restrict the mechanical constraints on their manipulation and bonding, to avoid stresses which could destroy the polarisation specificity of the component. A low-stress pick and place technology using a mask aligner has been employed. Eight hundred and fifty nanometres top-surface emitting GaAs/AlGaAs VCSELs, InGaAs/InP p–i–n photodiode arrays, and high-frequency CMOS silicon driver chips have been hybridised on silicon motherboards using this technology. The factors influencing the choice of bonding materials and the sequence of component hybridisation, including the requirements of subsequent planarisation and wiring processes, are discussed. The sources of alignment error are reported. Examples of working emitters, detectors and driver circuitry hybridised using this technology are presented.