Optical Backplane Research Articles

BPA to investigate optical backplanes

BPA to investigate optical backplanes

An 8-Gb/s optical backplane bus based on microchannel interconnects: design, fabrication, and performance measurements

We describe the characteristics of a microchannel-based optical backplane including signal-to-noise ratio (SNR), interconnect distances, and data transfer rates. The backplane employs 250 /spl mu/m-spacing two-dimensional (2-D) vertical cavity surface emitting lasers (VCSELs) and a microlens array to implement 500 /spl mu/m-, 750 /spl mu/m-, and 1-mm optical beam arrays. By integrating the transmitter and a multiplexed polymeric hologram as a deflector/beam-splitter for the guided-wave optical backplane, the result demonstrates a multibus line architecture and its high-speed characteristics. Maximum interconnect distances of 6 cm and 14 cm can be achieved to satisfy 10/sup -12/ bit error rate (BER) using 2/spl times/2 beams of 500 /spl mu/m- and 1 mm-spacing array devices. The total data transfer rate of the developed backplane has shown 8 Gb/s from eye diagram measurements.

Polymer waveguide devices with passive pigtailing: an application of LIGA technology

A combination of precision mechanics and LIGA has been used to realize metallic three-level tools for compression molding of transparent thermoplastic polymers. These tools enable the production of waveguide preforms and fiber positioning grooves in the same process step. In this way, a time-consuming active pigtailing can be avoided because the necessary precision of 1 μm is reached in all dimensions of the tool. A second polymer material, usually a casting resin or optical adhesive, is used as a waveguide core material, immersion medium and to fix the cover plate of the device simultaneously. As a first waveguide component a six-fold array of 4×4 multimode star couplers is presented that has been realized with PMMA and COC substrate materials. After production and qualification of a series of 300 of these devices the average excess loss is found better than 3 dB and the uniformity in the range of 2–3 dB. The main application of this device are optical backplanes for high-speed computers, but the technology allows for many other future components in the tele-and datacom field as well as in sensorics. Two further examples, a waveguide-based flow sensor head and a thermo-opto-optical switch are presented shortly.

Crosstalk and interconnection distance considerations for board-to-board optical interconnects using 2-D VCSEL and microlens array

We describe the design and experimental characterization of a substrate-mode optical backplane using 0.5-, 0.75- and 1-mm spacing two-dimensional (2-D) optical beam arrays. The system uses arrays of multiplexed holograms to implement free space board-to-board interconnects, and employs 250-/spl mu/m pitch 2-D vertical-cavity surface-emitting lasers (VCSEL) and microlens array as a transmitter to provide 0.5- to 1-mm spacing 2-D beam array, operating at 850 nm. By comparing the optical beam properties at the detector plane including the spot size and power uniformity of the optical beam array, as well as signal-to-noise ratio (SNR), the maximum interconnect distances are justified. Furthermore, we point out the improvement of the throughput that can be achieved by 2D crosstalk analysis within the same design concept. The results of crosstalk analysis obtained here can be used for application to the standard five-board free-space optical backplane system.

Novel Optical Backplane for Automotive Applications

Abstract Deep etch lithography like the LIGA technique combines high precision and mass production capability. It is a well suited candidate for precision micro-optics because of its unique characteristic which allows the fabrication of optical and mechanical micro-elements in the same substrate. In this paper we will focus on a novel alignment tolerant optical backplane approach well suited for automotive applications that is based on a hybrid integration of guided wave and free space micro-optics by the LIGA technique.

Optical backplanes with integrated polymer waveguides

Optical backplanes with integrated polymer waveguides

Three-dimensionally interconnected multi-bus-line bidirectional optical backplane

The concept of a three-dimensionally interconnected optical backplane for a high-performance system containing multichip module boards, operating at 850 nm, is introduced. The backplane reported here employs 2-D vertical-cavity surface-emitting lasers (VCSELs) and pho- todetector arrays as transceivers. By integrating 250-mm-pitch 2-D VC- SELs, microlenses, and photodetector arrays into our backplane design, we have demonstrated a multi-bus-line optical backplane and experi- mentally realized this architecture with 2-D VCSEL and detector arrays while using the third dimension as the signal-propagating direction. Such an approach greatly increases the aggregate bandwidth of the back- plane. Packaging issues such as misalignment, cross talk, and signal-to- noise ratio are studied. Eye diagrams up to 1.5 GHz were obtained with clear eyes, and the frequency response of a single bus line shows a bandwidth of 2.5 THz. © 1999 Society of Photo-Optical Instrumentation Engineers. (S0091-3286(99)00409-2)

Three-dimensionally interconnected bidirectional optical backplane

The concept of a three-dimensionally interconnected bidirectional optical backplane for a high performance system containing multichip module boards is introduced. The backplane reported here employs one-dimensional (1-D) and two-dimensional (2-D) vertical-cavity surface-emitting laser (VCSEL), and photodetector arrays as transceivers. By integrating VCSEL, lens, doubly multiplexed holographic gratings, and photodetector arrays, we have demonstrated this architecture while using the third dimension as the signal propagating direction. Packaging related issues such as misalignment, crosstalk, and signal-to-noise ratio are studied. The frequency response of our device shows a bandwidth of 2.5 THz. Eye diagrams for a single bus line up to 1.5 GHz are demonstrated with clear eyes. An aggregate bandwidth of 6 GHz is thus confirmed with 2/spl times/2 bus lines.

Field-programmable smart-pixel arrays: design, VLSI implementation, and applications

A smart-pixel array is a two-dimensional array of optoelectronic devices that combine optical inputs and outputs with electronic processing circuitry. A field-programmable smart-pixel array (FP-SPA) is a smart-pixel array capable of having its electronic functionality dynamically programmed in the field. Such devices could be used in a diverse range of applications, including optical switching, optical digital signal processing, and optical image processing. We describe the design, VLSI implementation, and applications of a first-generation FP-SPA implemented with the 0.8-microm complementary metal-oxide semiconductor-self-electro-optic effect device technology made available through the Lucent Technologies-Advanced Research Projects Agency Cooperative (Lucent/ARPA/COOP) program. We report spice simulations and experimental results of two sample applications: In the first application, we configure this FP-SPA as an array of free-space optical binary switches that can be used in optical multistage networks. In the second, we configure the device as an optoelectronic transceiver for a dynamically reconfigurable free-space intelligent optical backplane called the hyperplane. We also describe the testing setup and the electrical and the optical tests that demonstrate the correct functionality of the fabricated device. Such devices have the potential to reduce significantly the need for custom design and fabrication of application-specific optoelectronic devices in the same manner that field-programmable gate arrays have largely eliminated the need for custom design and fabrication of application-specific gate arrays, except in the most demanding applications.

Error and flow control in terabit intelligent optical backplanes

The design of a free-space optical backplane which supports error and flow control functions is described. Traditionally, these functions are implemented in custom high-speed electronic application specific integrated circuits, which are physically removed from the optical interconnect layer. In this paper, we consider migrating these functions directly into the optoelectronic layer, yielding an "intelligent optical backplane." Conventional error control protocols are infeasible with optical backplanes since they require excessive amounts of hardware. The design of an efficient error control protocol based upon a multidimensional parity check, along with the effective flow control protocol is proposed and analyzed. The key blocks of the protocol have been implemented in 0.8- and 0.5-/spl mu/m CMOS/SEED devices and are summarized. The protocols require significantly less hardware than alternative schemes, and smart pixel arrays supporting these protocols are scalable to higher bandwidths and lower latencies. A very large scale integration analysis indicates that using 2004 technology, a free-space backplane can potentially be clocked at 1 GHz and support 24 Tb/s of bandwidth. Finally, the proposed error control protocols should be useful in optical disks and holographic memory systems, which also perform error control on large two-dimensional arrays of optical bits.

Design, implementation, and characterization of a hybrid optical interconnect for a four-stage free-space optical backplane demonstrator

A four-stage unidirectional ring free-space optical interconnect system was designed, analyzed, implemented, and characterized. The optical system was used within a complementary metal-oxide semiconductor-self-electro-optic-effect-device-based optical backplane demonstrator that was designed to fit into a standard VME chassis. This optical interconnect was a hybrid microlens-macrolens system, in which the microlens relays were arranged in a maximum lens-to-waist configuration to route the optical beams from the optical power supply to the transceiver arrays, while the macrolens optical relays were arranged in a telecentric configuration to route optical signal beams from stage to stage. The following aspects of the optical system design are discussed: the optical parameters for the hybrid optical system, the image mapping of the two-dimensional array of optical beams from stage to stage, the alignment tolerance of the hybrid relay system, and the power budget of the overall optical interconnect. The implementation of the optical system, including the characterization of optical components, subsystem prealignment, and final system assembly, is presented. The two-dimensional array of beams for the stage-to-stage interconnect was adjusted with a rotational error of <0.05 degrees and a lateral offset error of <3.5 mum. The measured throughput is in good agreement with the lower-bound predictions obtained in the theoretical results, with an optical power throughput of -20.2 dB from the fiber input of the optical power supply to the modulator array and -25.5 dB from the fiber input to the detector plane.

In situ measurement of misalignment errors in free-space optical interconnects

A nonobtrusive technique for measuring misalignment errors in multistage free-space optical interconnects is proposed. The technique makes use of dedicated microoptics to relay higher order dedicated alignment beams generated by an optical power supply onto alignment detectors located on the periphery of a smart pixel chip. An implementation of this technique for measuring lateral (x-y) misalignment error in a multistage optical backplane demonstrator is then presented. Performance parameters are analyzed and future directions such as photonic extensions to electronic boundary scan standards are suggested.

Optical backplane with free-space optical interconnections using tunable beam deflectors and a mirror for bookshelf-assembled terabit per second class asynchronous transfer mode switch

We have designed an optical backplane with free-space optical interconnections using tunable beam deflector arrays and a mirror for terabit per second class bookshelf-assembled asynchronous transfer mode (ATM) switches. Optical beam transmitter arrays and optical beam receiver arrays are placed on the edges of a printed circuit board. Optical beams are deflected individually by the tunable deflector arrays, emitted obliquely and downward, and reflected at the mirror placed on the backplane, passing through some printed circuit boards, and reach the targeted receivers on the edges of printed circuit board. As a preliminary experiment, we show that board-to-board free-space arbitrary optical interconnections are possible using a tunable beam deflector array and 1-mm-pitch 2×2 optical beam array provided with a vertical cavity surface emitting laser diode, we also show that these optical interconnections are made very stable by attaching reinforcing frames to the printed circuit board. Furthermore, we show that more than 1000 channel interconnections per printed circuit board are possible using a 1-mm-pitch optical beam array. As the speed per channel may be more than 1 Gbit/s, the throughput of the interconnection per board reaches almost the terabit/s level. Using this optical interconnection system is used, ATM switches with a huge capacity of 1.0 to 10 Tbit/s will be possible. © 1998 Society of Photo-Optical Instrumentation Engineers.

Design, implementation, and characterization of an optical power supply spot-array generator for a four-stage free-space optical backplane

The design and implementation of a robust, scalable, and modular optical power supply spot-array generator for a modulator-based free-space optical backplane demonstrator is presented. Four arrays of 8 x 4 spots with 6.47-mum radii (at 1/e(2) points) pitched at 125 mum in the vertical direction and 250 mum in the horizontal were required to provide the light for the optical interconnect. Tight system tolerances demanded careful optical design, robust optomechanics, and effective alignment techniques. Issues such as spot-array generation, polarization, power efficiency, and power uniformity are discussed. Characterization results are presented.

Optomechanics for a four-stage hybrid-self-electro-optic-device-based free-space optical backplane

We present the design, fabrication, and testing of optomechanics for a free-space optical backplane mounted in a standard 6U VME backplane chassis. The optomechanics implement an optical interconnect consisting of lenslet-to-lenslet, as well as conventional lens-to-lens, links. Mechanical, optical, electrical, thermal, material, and fabrication constraints are studied. Design trade-offs that affect system scalability and ease of assembly are put forward and analyzed. Novel mounting techniques such as a thermal-loaded interference-fitted lens-mounting technique are presented and discussed. Diagnostic tools are developed to quantify the performance of the optomechanics, and experimental results are given and analyzed.

Connection cube modules for optical backplanes and fiber networks

A modular free-space optical system, called the connection cube, for connecting arrays of electro-optic transceivers and fiber-array connectors is presented. The connection cube module provides bidirectional data transfer between four processing nodes on a cube face and can be used as a basic building block for optical backplanes and interconnect networks. An experimental system for connecting four processing nodes is presented and used to examine alignment and packaging issues. An analysis of the dimensional requirements and scaling capability for systems based on this module is conducted. This analysis shows that, when the connection cube module is adapted to vertical-cavity surface-emitting-laser-based point-to-point fiber-array links currently under development, it can connect up to 14 processing nodes with an aggregate data transfer capacity of 112 Gbits/s with 19.6-W power consumption.

Design and characterization of a microchannel optical interconnect for optical backplanes

The design, modeling, and experimental characterization of a microchannel-based free-space optical interconnect is described. The microchannel interconnect was used to implement a representative portion of an optical backplane that was based on field-effect transistor, self-electro-optic device smart-pixel transceivers. Telecentric relays were used to form the optical interconnect, and two modes based on two different optical window clusterings were implemented. The optical system design, including the optical geometry for different degrees of clustering of windows supported by a lenslet relay and the image mapping associated with a free-space optical system, is described. A comparison of the optical beam properties at the device planes, including the spot size and power uniformity of the spot array, as well as the effects of clipping and misalignment for the different operating modes, is presented. In addition, the effects of beam clipping and misalignment for the different operating modes is presented. We show that microchannel free-space optical interconnects based on a window-clustering scheme significantly increase the connection density. A connection density of 2222 connections/cm(2) was achieved for this prototype system with 2 x 2 window clustering.

Performance of an optical backplane bus for switch interconnection

The employment of an optical bus for the interconnection network of a switching system is investigated and the configuration of these interconnections is discussed. Using power budget analysis, it is shown that to maximise the number of positions for an amplified bus configuration, the number of taps between the amplifiers must be small, or amplification must be distributed within the bus. Crosstalk within cascaded bus arrays is examined and an ≈634 Gbits/s configuration of the MONET architecture is shown to be feasible.

A hybrid-SEED smart pixel array for a four-stage intelligent optical backplane demonstrator

This paper describes the VLSI design, layout, and testing of a Hybrid-SEED smart pixel array for a four-stage intelligent optical backplane. The Hybrid-SEED technology uses CMOS silicon circuitry with GaAs-AlGaAs multiple-quantum-well modulators and detectors. The chip has been designed based on the HyperPlane architecture and is composed of four smart pixels which act as a logical 4-bit parallel optical channel. It has the ability to recognize a 4-bit address header, inject electrical data onto the backplane, retransmit optical data, and extract optical data from the backplane. In addition, the smart pixel array can accommodate for optical inversions and bit permutations by appropriate selections of multiplexers. Initial data pertaining to the electrical performance of the chip will be provided and a complete logical description will be given.

An ATM-based intelligent optical backplane using CMOS-SEED smart pixel arrays and free-space optical interconnect modules

The architecture, smart pixel array chip design, and optical design of an intelligent free-space digital optical backplane for ATM switching are presented. The smart pixel chip uses reflective SEED (self-electrooptic effect device) optical modulators and detectors flip-chip bonded to CMOS circuitry. This chip is one of the most complex designs ever reported in this technology, and it operates at a simulated backplane clock rate of 125 MHz. The low-loss optical system employs f/4 diffractive minilenses and microlenses to interconnect clusters of smart pixels, and it is shown to allow 2060 connections per chip if 1-cm2-sized smart pixel chips are used. This gives a predicted bisection bandwidth of around 1 Tb/s across a 10-in circuit board edge for a full-sized system.