Operational Transconductance Amplifier Research Articles

Electronically tunable positive and negative fractional order inductor circuit using single topology

This article presents electronically tunable grounded and floating fractional order inductor circuits. The proposed circuits employ two operational transconductance amplifiers (OTAs), one fractional order capacitor, one inverter and four MOS switches and are capable to work in positive mode and negative mode without change in topology. The behaviour of the proposed circuit is also analyzed in presence of parasites that may appear in the practical circuit. The functional verification is done via pre and post layout simulations at 90 nm CMOS technology parameter. The usefulness of the proposed positive fractional inductor circuit is demonstrated through fractional order band pass filter and fractional order high pass ladder filter. The performance of the proposed negative fractional inductance circuit is demonstrated through a fractional inductance cancellation circuit.

Resistorless First-Order Universal Filter Structures Employing OTAs with Independent Controllability of Gain and Pole Frequency

This communication presents two new first order universal active filter configurations employing operational transconductance amplifiers (OTA) and use grounded capacitor which is prominently suitable for integrated chip (IC) fabrication. One of the proposed topologies provides voltage mode (VM) and transconductance mode (TCM) of operations while the other circuit provides current mode (CM) in addition with transresistance mode (TRM) filter functions. All three first order filter functions namely low pass filter (LPF), high pass filter (HPF) and all pass filter (APF) are configurable with appropriate choice(s) of input voltage/current signals. An equal transconductor condition (which can be easily achieved) is required for the realization of APF functions. The proposed filter configurations possess high input impedance and high output impedance and also offer independent electronic tunability of pole frequency/cut-off frequency. The gain of filters realized in VM, TCM and TRM has independent electronic tunability feature and can be adjusted through transconductor. For the usability of proposed filters, multi-phase sinusoidal oscillator has also been demonstrated. To assure the workability of the proposed filter structures, PSPICE simulations with CMOS OTA implemented in 0.18 µm TSMC technology parameters has been used. Various simulation results including Monte-Carlo simulations, process corner analysis, total harmonic distortions (%THD) and temperature analysis have also been appended. Experimental results employing off-the-shelf IC LM13700 type OTAs have also been included to verify the theoretical propositions of first order universal filters and multiphase sinusoidal oscillators.

A Lossless Active Inductor Design Using Single ZC-VDCC: Grounded and Floating Mode

This research paper includes two different topologies for the operation of both grounded and floating active inductor (AI) realization. Both structures use a single Z-Copy Voltage Differencing Current Conveyor (ZC-VDCC) and an external grounded capacitor (C). The operational behavior of the proposed design is free from the component matching constraint. In addition, an application workability of the AI is tested for filter frequency response that comprises band pass filter (BPF) and band rejection filter (BRF) using grounded as well as floating active inductor, respectively. The performance test of the proposed active inductor is successfully validated in SPICE computer simulation using 0.18 µm TSMC parameter for ZC-VDCC. Moreover, an experimental verification is also performed using easily available Current Feedback Operational Amplifier (CFOA/IC-AD844) and Operational Transconductance Amplifier (OTA/IC-CA3080) for the implementation of ZC-VDCC. Both simulation and experimental observation are well verified to justify the theoretical concept behind the proposed AI.

New memristor-less, resistor-less, two-OTA based grounded and floating meminductor emulators and their applications in chaotic oscillators

This paper presents a simple realization of the meminductor emulator using two operational transconductance amplifiers (OTAs) and two capacitors. To obtain different configurations of meminductor in the proposed design, one of the OTA has been replaced by a multi-output transconductance amplifier (MO-OTA). MO-OTA is a slightly modified version of conventional OTA that has multiple outputs. The design flexibilities offered by MO-OTA helped in achieving decremental as well as incremental configurations for both grounded and floating meminductor emulators. The proposed meminductor emulator realizations are very simple because these emulators do not employ an analog multiplier, resistor, or memristor. The pinched hysteresis curves have been acquired for the frequency range of 600 kHz–900 kHz for different values of capacitors. The proposed meminductor emulators have been designed and simulated with the help of the LTspice tool using TSMC 180 nm CMOS technology parameters. The pinched hysteresis loops, transient analysis, and non-volatility tests of the proposed meminductor emulators confirm their satisfactory behavior as meminductor. The functioning of proposed meminductor emulator circuits has also been tested by demonstrating their use in chaotic oscillators.

Impedance-mode capacitance multiplier with OTA-based flipped voltage follower for high accuracy and large multiplication factor

A capacitance multiplier with large multiplication factor, increased accuracy, and class AB operation is presented. The multiplier is an impedance mode implementation consisting of a Flipped Voltage Follower based on Operational Transconductance Amplifiers (OTA). This gives the possibility to offer rail-to-rail operation and class AB operation to drive demanding loads depending on the application. In addition, one of the OTAs is designed to offer a transconductance gain based on passive resistors and achieve increased accuracy in the multiplication factor by means of proper layout techniques. The circuit was implemented in a 0.5µm technology and has multiplication factors of 10, 100, 1k and 10k, a power dissipation of 0.56mW and a silicon area of 0.059mm2. Simulation and experimental results of the multiplier demonstrate the proper operation.

A 0.7V 1.6mW fractional-N synthesizers for BLE RF transceiver in 40nm CMOS

This paper presents a low-power fractional-N synthesizer for BLE with a gate-switching charge pump (CP) and high-speed prescaler. To reduce the current mismatch under low supply voltage, a master-slave rail-to-rail operational trans-conductance amplifier (OTA) structure is employed to the CP; Current self-matching technique guarantees the charging current is equal to discharging current. The embedded logic gates and power switch technique are employed to true-single-phase-clock (TSPC) to reduce power consumption and improve the operating speed of the divider. Random dither is injected into the ΔΣ modulator to prolong the period of output sequence. The proposed phase-locked loop (PLL) is implemented in the 40-nm CMOS process. It achieves -85.94dBc/Hz@100kHz and -109.18dBc/Hz@1MHz in fractional-N mode while consuming 1.6mW under a 0.7V voltage supply.

Design methodology for general enhancement of a single-stage self-compensated folded-cascode operational transconductance amplifiers in 65 nm CMOS process

The problems resulting from the use of nano-MOSFETs in the design of operational trans-conductance amplifiers (OTAs) lead to an urgent need for new design techniques to produce high-performance metrics OTAs suitable for very high-frequency applications. In this paper, the enhancement techniques and design equations for the proposed single-stage folded-cascode operational trans-conductance amplifiers (FCOTA) are presented for the enhancement of its various performance metrics. The proposed single-stage FCOTA adopts the folded-cascode (FC) current sources with cascode current mirrors (CCMs) load. Using 65 nm complementary metal-oxide semiconductor (CMOS) process from predictive technology model (PTM), the HSPICE2019-based simulation results show that the designed single-stage FCOTA can achieve a high open-loop differential-mode DC voltage gain of 65.64 dB, very high unity-gain bandwidth of 263 MHz, very high stability with phase-margin of 73°, low power dissipation of 0.97 mW, very low DC input-offset voltage of 0.14 uV, high swing-output voltages from −0.97 to 0.91 V, very low equivalent input-referred noise of 15.8 nV/Hz, very high common-mode rejection ratio of 190.64 dB, very high positive/negative slew-rates of 157.5/58.3 V⁄us, very fast settling-time of 5.1 ns, high extension input common-mode range voltages from −0.44to 1 V, and high positive/negative power-supply rejection ratios of 75.5/68.8 dB. The values of the small/large-signal figures-of-merits (𝐹𝑜𝑀s) are the highest when compared to other reported FCOTAs in the literature.

Simulation Based Analysis of Low-Voltage-Tunable Biquad Filter Using Operational Transconductance Amplifiers

ABSTRACT A CMOS realisation of a voltage tunable biquad filter using only MOSFET-based operational transconductance amplifier (OTA) and capacitors has been designed using silicon-based CMOS technology. It operates at a low supply voltage of 0.25 V at a 500 MHz frequency. The filter is theoretically analysed and then simulated using commercially available Cadence Virtuoso tools at 0.18 μm CMOS technology parameters. The proposed design is used to implement second-order low pass, highpass, bandpass, and bandreject filters with the same circuit simply by tuning the input voltage. The bandwidth and cut-off frequency also can be changed by changing the capacitor values.

Synthetic Transformer using Operational Transconductance Amplifier (OTA) and Voltage Differencing Current Conveyor (VDCC)

This paper presents a new realization of synthetic transformer using off the shelf active blocks. This proposed transformer is designed using operational transconductance amplifier (OTA), voltage differencing current conveyor (VDCC), resistor and capacitor. Use of VDCC helps to utilizes benefits of both voltage differencing unit and current conveyor. The working of proposed circuit is verified through simulations in LTSPICE using TSMC 180nm process characteristics. The proposed circuit offers the feature of adjusting primary and secondary self-inductances and mutual inductance independently. The bias current of the VDCC is used to control the primary and secondary self-inductance and mutual inductance of synthetic transformer.

Retraction Note: Design of three stage cascaded low power CMOS operational trans conductance amplifier (OTA) for ECG applications

Retraction Note: Design of three stage cascaded low power CMOS operational trans conductance amplifier (OTA) for ECG applications

A Modern VDCCTA Active Element and Its Electronic Application

In this paper, a novel current mode (CM) building block termed Voltage differencing current conveyor transconductance amplifier (VDCCTA) is developed by combining the voltage differencing current conveyor (VDCC) and an operational transconductance amplifier (OTA). This modern active block VDCCTA is extended for applications such as a lossless inductor, filter design, and chaotic circuit design. An active inductor simulator (AIS) without any component matching is designed using the proposed VDCCTA block and a grounded capacitor as a first application that offers flexibility to model grounded positive active inductor (GPAI), grounded negative active inductor (GNAI), and floating positive active inductor (FPAI) circuits. Moreover, the proposed positive active inductor (PAI) can also be translated for multiple input single output (MISO) voltage mode (VM) universal filter with two external passive elements and chaotic circuitry. The characteristics of VDCCTA are verified with the CM multifunction filter, VM band-pass filter, and VM-MISO filter. A complete exercise of this newly reported VDCCTA block is analyzed for their port characteristics validation and the performance parameters using PSPICE simulation. Finally, experimental verification of the proposed AIS is tested to justify the theoretical and simulated results.

Tunnel-FET Evolution and Applications for Analog Circuits

In this work different generations of field effect tunneling transistor (TFET) are evaluated through DC digital and analog figures of merits. For TFET devices the main digital figure of merit is the subthreshold slope (SS), while for analog application the intrinsic voltage gain (AV) is the most important one. For the early generations, that are based on silicon, the SS does not reach values smaller than 60mV/dec at room temperature, however, the AV reaches values up to 80 dB, showing to be promising for analog applications. As the TFETs were being optimized for digital applications and consequently presenting better switching performance, the intrinsic voltage gain moves in the opposite direction. This opposite trend is related to which transport mechanism is predominant for each type of device. While III-V TFETs are more dependent on Band to Band Tunneling (BTBT), silicon devices are more relying on Trap-Assisted Tunneling (TAT). While BTBT allows for faster switching, TAT is less dependent on the drain electric field, so the former favors SS while the latter favors AV. Based on the good analog behavior of silicon channel TFETs, a two-stage operational transconductance amplifier (OTA) was designed with different TFET technologies and the compared results were discussed.

Design of a Configurable Third-Order Gm-C Filter Using QFG and BD-QFG MOS-Based OTA for Fast Locking Speed PLL

High-speed PLL is highly demanding with the advancement in the VLSI market. PLL performance gets affected due to bandwidth limitation. This paper presents third-order configurable transconductance capacitance ([Formula: see text]-[Formula: see text])-based loop filter for high-speed PLL. Operational transconductance amplifier (OTA) serves as a basic cell of the [Formula: see text]-[Formula: see text] filter. Quasi-floating gate (QFG) and Bulk-driven qausi-floating gate (BD-QFG) MOS-based differential input folded cascode (FC) OTAs are proposed for low-voltage operation. Here, DC gain of the BD-QFG FC OTA enhanced 5.18% than QFG FC OTA. The proposed OTAs enhanced DC gain, CMRR, UGB and FOM along with reduction in the power consumption in comparison to the state-of-art work. Further, third-order [Formula: see text]-[Formula: see text] filters are designed using both QFG and BD-QFG MOS-based OTAs and achieved [Formula: see text]3[Formula: see text]dB cut-off frequency of 16.51[Formula: see text]MHz and 17.22[Formula: see text]MHz, respectively. The proposed QFG and BD-QFG MOS-based filters achieved 22.42% and 21.53% reduction in power than the reported result, respectively. The locking time of integer-N PLL is calculated as 0.33[Formula: see text][Formula: see text]s and 0.32[Formula: see text][Formula: see text]s, respectively, through an analytical approach. The transistor-level simulation has been done in 0.18[Formula: see text][Formula: see text]m CMOS process.

A 96.9-dB-Resolution 109-μW Second-Order Robust Closed-Loop VCO-Based Sensor Interface for Multiplexed Single-Ended Resistance Readout in 180-nm CMOS

This article presents a highly digital robust voltage-controlled oscillator (VCO)-based front end for multiplexed single-ended resistive sensor readout applications. The architecture features a modified digital phase-locked loop (DPLL) structure that enables second-order noise shaping without any operational transconductance amplifiers (OTAs) and a single feedback digital-to-analog converter (DAC). The direct conversion of the sensor input resistance to time-domain information obviates the need for any conditioning circuit, thus resulting in a highly digital and area-compact architecture. The closed loop substantially reduces the amplitude of the signal at the VCO input, thereby achieving high linearity. To ensure high robustness against supply and temperature variations, a double measurement approach is employed. Fabricated in a 180-nm CMOS process with a 0.1-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area, the sensor readout consumes 109 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> of power and achieves a resolution of 96.9 dB for 0.5-ms conversion time, resulting in a Schreier figure of merit (FoM) of 166.5 dB. The circuit only requires a cheap and efficient single-point trimming calibration at room temperature. The low conversion time enables multiplexing among multiple sensor readouts. The supply and temperature sensitivities are 0.4%/V and 36 ppm/°C, respectively.

A novel voltage-mode universal second-order filter using five single ended OTAs and its quadrature sinusoidal oscillator application

This study proposes a single-ended operational trans-conductance amplifier (SEOTA)-based triple inputs and single output high-input impedance voltage-mode (VM) universal second-order filter. The proposed universal VM SEOTA-based second-order filter can be realized for the non-inverting low-pass, non-inverting high-pass, non-inverting band-reject, non-inverting all-pass and inverting band-pass filtering functions by appropriately using different triple-input voltage signals. The high-input impedances of the proposed universal VM SEOTA-based configuration enable the second-order filter to be cascaded without additional buffers. The proposed configuration does not employ external resistors and accordingly is an active SEOTAs and capacitors (SEOTA-C) universal second-order filter. The proposed circuit using two grounded capacitors which is more apposite to further develop into an integrated circuit implementation. The resonance angular frequency and quality factor are orthogonal electronically adjustable. By slightly modifying the proposed universal VM SEOTA-based second-order filter configuration, the VM SEOTA-C quadrature sinusoidal oscillator is achieved. The oscillation frequency and the oscillation condition of the quadrature sinusoidal oscillator can be independently and electronically tuned by adjusting the bias currents of two SEOTAs. PSpice simulation results confirmed theoretic anticipation. The result of the experiment of the commercially available SEOTAs, LT1228s, are also used to verify the characteristics of the proposed universal VM SEOTA-based second-order filter and VM SEOTA-based quadrature sinusoidal oscillator.

Analog Signal Processing Using Current Mode Computational Circuits

In this study, enhanced linearity and wide linear range current adder and subtractor circuits based on cascode current mirrors are presented. Among other analogue signal processing devices, the described circuits can be employed in operational transconductance amplifiers (OTA), Gm-C filters, and amplifiers. To enhance current mirroring performance, the suggested circuits use the cascode current mirror topology. A 1.8-volt supply and TSMC 0.18-micron CMOS technology were used to model the suggested circuits. The suggested circuits have an allowed error percentage of less than 2.5% and perform well in the current range of 0 to 80 A. The outcomes of the SPICE simulation have shown how well the proposed circuits work.

0.4-V, 81.3-nA Bulk-Driven Single-Stage CMOS OTA with Enhanced Transconductance

The paper describes a single-stage operational transconductance amplifier suitable for very-low-voltage operation in power-constrained applications. The proposed circuit avoids the tail current generator in the differential pair while preventing pseudo-differential operation. Moreover, the adoption of positive feedback allows increasing the stage transconductance while minimizing the current consumption. Experimental measurements on prototypes implemented in a standard CMOS 180-nm technology, show superior performance as compared to the state of the art.

High-complex chaotic system based on new nonlinear function and OTA-based circuit realization

This research proposes a chaotic system using a new modified rectangular nonlinear function based on the principle of the third-order jerk concept. The dynamic behaviors can be realized by manipulating only one parameter from periodic, non-periodic, single-scroll, and double-scroll attractors. The proposed chaotic system can achieve relatively high-complexity chaotic behavior, as evident in the comparatively high Kaplan-Yorke dimension (DKY = 2.43) with the existing jerk systems. The performances of the proposed chaotic system are also computed and simulated through the MATLAB numerical analysis, including scenarios of bifurcations branches, Lyapunov exponents, route to chaos, phase portraits, 0–1 test charts, and Poincaré map. The proposed system analyzes the coexistence of asymmetric or symmetric attractors confirmed with basins of attraction to highlight the presence of multiple attractors, which influence initial conditions. In addition, the system's offset boosting and amplitude control are included. Furthermore, a double-scroll attractor and a four-scroll attractor can also be achieved by placing nonlinear functions at different positions in the third-order system., The circuits of the proposed chaotic systems can be conveniently realized using commercially available operational transconductance amplifiers (OTAs) and capacitors. The performances of the circuit are also proven through the experimental results compared with the numerical results. The experimental results exhibit the ease of construction based on the new nonlinear function and are suitable for applying in the data encryptions.

Miller compensated four-stage OTA with Q-reduction for wide range of load capacitors

This paper proposes a four-stage miller compensated Operational Transconductance Amplifier (OTA) with Q-reduction. The multi-stage OTA is an ideal choice for the submicron CMOS technology. The main challenge in multi-stage OTA design with low quiescent current is the increased number of high impedance nodes. These high impedance nodes create stability issues. Usually, the multi-stage OTA requires the compensation capacitor in the order of pF which consumes more chip area; moreover, it reduces the bandwidth of the OTA. The proposed four-stage OTA uses a single miller capacitor Cm along with a feed-forward capacitor Cf. The four-stage OTA uses only 500fF of total compensation capacitors to stabilize a complex four-stage OTA. The proposed OTA uses multiple feed-forward paths to enhance the small-signal and the large-signal performances of the OTA. The four-stage OTA achieves a better transient response with the settling time of 510ns under low quiescent power of 63.6μW for the wide range of load capacitors of 5pF to 100pF.

A 1–3 GHz CMOS mixer-first receiver frontend with dual-feedback OTA achieving 306 MHz IF bandwidth, 2.1 dB NF, and 33 dB gain

In this paper, a mixer-first receiver frontend with dual-feedback baseband is proposed. The negative resistive and positive capacitive feedback paths are both applied to single-stage inverter-based operational transconductance amplifier (OTA) with fewer poles, to cover a wide BB frequency range. The [Formula: see text]-path filtering at the RF side and second-order filtering at the BB side inhibit out-of-band blocker interferences. The receiver frontend is designed in 65 nm CMOS. Simulation results display an NF of 2.1 dB across 306 MHz IF bandwidth, and a maximum gain of 33 dB from 1 to 3 GHz LO frequency range. The in-band and out-of-band IIP3 are -13 and 16 dBm, respectively. The receiver core draws 40 mW at 1 GHz LO frequency.