Operational Transconductance Amplifier Research Articles

Low power three-stage OTA using reverse nested frequency compensation without nulling resistor

This study introduces a novel reverse nested miller compensated high gain three stage operational transconductance amplifier (OTA) that exhibits lower power consumption and maximum allowable voltage swing. In this context, two amplifiers have been employed. The initial amplifier employs PMOS as the primary amplifying component, with a specified IDD value of 200 A. In the subsequent stages, both the second and third amplifiers are biased to operate at a current level of 2 times IDD. These operations are conducted within a 45 m Cadence Virtuoso environment. The other three-stage amplifier employs PMOS as the primary amplifier, with a bias current (IDD) of 4 μA. In a 90 m Cadence Virtuoso environment, both the second and third stages are biased to operate at a current of 5 times IDD. The primary design criteria introduced in this design approach are gain, phase margin, and power consumption, which are thoroughly stated. The circuits undergo Monte Carlo and corner evaluations, and the findings are deliberated about in the conclusion of the research. In order to attain the greatest allowable voltage swing, these amplifiers are fabricated with VDD values of 500 m and 900 m. The output voltage is set to a constant value of VDD/2.

A 10-kHz BW 104.3-dB DR discrete-time delta-sigma modulator with ring-amplifier-based integrator

This paper presents a 3rd-order discrete-time delta-sigma modulator (DT DSM) with ring-amplifier-based integrators. To fulfill the performance requirement of the switched-capacitor (SC) integrator for the DSM with low power consumption, a dynamic ring amplifier is employed to replace the conventional continuous-time operation transconductance amplifier (OTA) in the integrator. The offset and 1/f noise of the 1st-stage integrator are further suppressed with an auto-zero structure. The quantizer is realized by a 3-bit flash analog-to-digital converter (ADC) to reduce the quantization noise power, while the mismatch in the feedback digital-to-analog converter (DAC) is suppressed by a dynamic weighting averaging (DWA) circuit. The DT DSM prototype is fabricated with a 0.18-μm CMOS process with an active area of 1.39 mm2, achieving 99.3 dB SNDR and 104.3 dB DR with a signal bandwidth of 10 kHz and an oversampling ratio of 128. The power consumption is 963.9 μW under a 3.3V power supply, corresponding to a Schreier figure-of-merit(FoMs) value of 174.5 dB.

Design of a high bandwidth ECG signal low noise amplifier circuit for wearable devices

Nowadays, more than one million people die due to heart problems annually. Detecting the Electrocardiogram curve is an effective way to evaluate heart condition. Compared with large devices in the hospital, wearable devices are showing their advantage in detecting peoples Electrocardiogram whenever and wherever possible. However, in traditional amplifier circuit design, there is less attention to the bandwidth. The noise is negatively correlated with the current while the power consumption is positively correlated with the current, so it is challenging to balance the noise and power. Therefore, a design of a high bandwidth Electrocardiogram signal low noise amplifier circuit for wearable devices is proposed in this paper. The improved circuit is based on a conventional instrumentation amplifier and consists of two stages. The op-amps were replaced with Operational Transconductance Amplifier. The circuit also has a Driven-Right-Leg circuit part, which can tremendously reduce the effect of common-mode noise. The simulation result shows that the circuit has a high bandwidth and stable gain. Meanwhile, the circuit consumes less power and has a low integrated input-referred noise. This study is extremely helpful in expanding the application of wearable Electrocardiogram signal-detecting devices.

Improvement in Sizing Constrained Analog IC via Ts-CPD Algorithm

In this work, we propose a variation of the cellular particle swarm optimization algorithm with differential evolution hybridization (CPSO-DE) to include constrained optimization, named Ts-CPD. It is implemented as a kernel of electronic design automation (EDA) tool capable of sizing circuit components considering a single-objective design with restrictions and constraints. The aim is to improve the optimization solutions in the sizing of analog circuits. To evaluate our proposal’s performance, we present the design of three analog circuits: a differential amplifier, a two-stage operational amplifier (op-amp), and a folded cascode operational transconductance amplifier. Numerical simulation results indicate that Ts-CPD can find better solutions, in terms of the design objective and the accomplishment of constraints, than those reported in previous works. The Ts-CPD implementation was performed in Matlab using Ngspice and can be found on GitHub (see Data Availability Statement).

A low-power low-noise amplifier with high CMRR for wearable healthcare applications

Low-noise and low-power operation are important parameters of amplifier intended for wearable healthcare applications. However, along with these parameters the amplifier must be able to deliver high Common Mode Rejection Ratio (CMRR) for mitigating the effect of 50/60 Hz interference. This paper reports capacitively coupled-capacitive feedback amplifier based on Self Cascode Current Mirror-II (SCCM-II) Operational Transconductance Amplifier (OTA). The obtained results for proposed SCCM-II OTA based amplifier shows gain of 39.79 dB, input referred noise of 2.64 μVrms, bandwidth of 0.794-343.4 Hz, area consumption of 0.154 μm2, power consumption of 2.54 μW with ±0.9 V supply. The noise efficiency factor and CMRR values for proposed amplifier are 3.87 and 122.1 dB, respectively. In-depth theoretical interpretations and mathematical modeling of amplifier are validated in 0.18μm standard CMOS process using BSIM3V3 MOS device models. The Gaussian distribution plots of proposed amplifier for 200 Monte-Carlo iterations infer mean values for gain and CMRR are 39.79 dB and 112.96 dB which are very close to their nominal values. The proposed amplifier has been compared with conventional approach as well as with literature and improvement in results is observed in terms of input referred noise, power and CMMR. These advantages of the proposed amplifier make it suitable for non-invasive wearable healthcare applications.

THE DESIGN OF HIGH EFFICIENCY AND LOW POWER SWITCHED OPAMP

The tendency of design of integrated circuits (ICs) goes to through the power and area reduction way. The surface area of very-large scale integrated circuits is shrinking along with the shrinking of technological dimensions. Power reduction requires usage of low-power design methodologies. The design of Switched-Opamp (SwOp) circuit based on typical Operational Transconductance Amplifier (OTA), with high efficiency is presented. Reduction of power consumption, using digitally controlled switches, is provided. The suggested SwOp was fabricated in a 14nm FinFET technology and achieved a DC gain of 38.4dB, a maximum operating frequency of 11.5GHz and a power consumption of 114.48uW for worst corner (SS) when the load capacitor is 5pF. The power consumption of proposed architecture is reduced about two times. Structure proposed in the paper can be integrated in modern analog-to-digital conversion application, high-speed receivers, memory systems.

Design of robust analog integrated circuit based on process corner performance variability minimization

A novel technique of performance optimization along with fabrication process variation tolerance of integrated circuits is proposed in this work. It is well-known that the probability of chip being manufactured under normal process environment is higher than the other corner process environments since it follows a Gaussian distribution. In this proposed approach Process Corner Performance Variability Minimization (PCPVM) is carried out simultaneously with performance optimization. In PCPVM the statistical performance deviations of the corner cases from the nominal case is minimized by considering the actual SPICE (Simulation Program with Integrated Circuit Emphasis) parameters of different process corners for performance evaluation. The proposed design is made robust by optimizing the circuit performance in nominal case and, also minimizing the difference between chip performances in nominal and worst case corner environments. This approach is expected to improve the performance of the ICs manufactured even under extreme process corner conditions. The proposed technique is validated in two example cases of current starved voltage controlled oscillator and Operational Transconductance Amplifier.

A Survey of Ultra-Low-Power Amplifiers for Internet of Things Nodes

This paper investigates CMOS operational transconductance amplifier (OTA) design methodologies suitable for Internet of Things nodes. The use of MOS transistors in the subthreshold of the body terminal for signal input or bias, as well as newer inverter- and digital-based techniques, is considered. Solutions from the authors’ work are utilized as main case examples. State-of-the-art ultra-low-power OTAs are then thoroughly compared using a data-driven approach. According to the findings, digital- and inverter-based solutions have the lowest area occupation and superior small-signal performance but are inherently susceptible to process, supply, and temperature (PVT) variations. The only “analog” approach suitable for a sub-0.6 V supply is body driving in conjunction with subthreshold bias. It offers competitive large-signal performance and, more importantly, is less sensitive to PVT variations at the expense of silicon area.

A miniature tunable quadrature shadow oscillator with orthogonal control

This article presents a new design of a quadrature shadow oscillator. The oscillator is realized using one input and two outputs of a second-order filter cell together with external amplifiers in a feedback configuration. The oscillation characteristics are controlled via the external gain without disturbing the internal filter cell, following the concept of the shadow oscillator. The proposed circuit configuration is simple with a small component-count. It consists of, two voltage-different transconductance amplifiers (VDTAs) along with a couple of passive elements. The frequency of oscillation (FO) and the condition of oscillation (CO) are controlled orthogonally via the dc bias current and external gain. Moreover, with the addition of the external gain, the frequency range of oscillation can be further extended. The proposed work is verified by computer simulation with the use of 180 nm complementary metal–oxide–semiconductor (CMOS) model parameters. The simulation gives satisfactory results of two sinusoidal output signals in quadrature with some small total harmonic distortions (THD). In addition, a circuit experiment is performed using the commercial operational transconductance amplifiers LM13700 as the active components. The circuit experiment also demonstrates satisfactory outcome which confirms the validity of the proposed circuit.

A 0.8 V, 14.76 nVrms, Multiplexer-Based AFE for Wearable Devices Using 45 nm CMOS Techniques.

Wearable medical devices (WMDs) that continuously monitor health conditions enable people to stay healthy in everyday situations. A wristband is a monitoring format that can measure bioelectric signals. The main part of a wearable device is its analog front end (AFE). Wearables have issues such as low reliability, high power consumption, and large size. A conventional AFE device uses more analog-to-digital converters, amplifiers, and filters for individual electrodes. Our proposed MUX-based AFE design requires fewer components than a conventional AFE device, reducing power consumption and area. It includes a single-ended differential feedback operational transconductance amplifier (OTA) and n-pass MUX-based AFE circuits which are related to the emergence of low power, low area, and low cost AFE-integrated chips that are required for wearable biomedical applications. The proposed 6T n-pass multiplexer measures a gain of -68 dB across a frequency range of 100 kHz with a 136.5 nW power consumption and a delay of 0.07 ns. The design layout area is approximately 9.8 µm2 and uses 45 nm complementary metal oxide semiconductor (CMOS) technology. Additionally, the proposed single-ended differential OTA has an obtained input referred noise of 0.014 µVrms, and a gain of -5.5 dB, while the design layout area is about 2 µm2 and was designed with the help of the Cadence Virtuoso layout design tool.

Analysis and design of a fourth-order ΣΔ ADC for MEMS digital gyroscope sensors

This paper presents a fourth-order sigma-delta (ΣΔ) ADC applied to a micro-electro-mechanical system (MEMS) gyroscope system. First, a system-level model of ΣΔ modulator containing non-ideal factors is established, and the optimal system performance of the ΣΔ modulator is determined by optimizing the feedforward path and the feedback coefficient of the feedback path. Then, the operational transconductance amplifier (OTA) with chopping technique and clock timing to control bias current in the first stage integrator of the circuit design is able to reduce not only the flicker noise of the modulator, but also reduce the system power consumption. Third, the design of other essential circuit modules is presented, and the circuit performance meets the requirements and low-power consumption is achieved. The designed ΣΔ ADC uses a 0.18 μm CMOS BCD process, with a ΣΔ modulator area of 0.64 mm2 and a digital filter area of 2.03 mm2. When the sampling frequency is 2 MHz and the signal bandwidth is 7.8 kHz, the experimental measurement results show that the proposed ΣΔ modulator with the fourth-order CIFF structure can achieve a signal-to-noise ratio (SNR) of 66.3 dB and an effective number of bits (ENOB) of 10.07 bits, with a dynamic range (DR) of 89 dB and a power consumption of 9 mW. The SNR of ΣΔ ADC after filtering is 63 dB, which meets the requirements of high DR and low-power consumption of MEMS digital gyroscope sensors.

Single-Stage Complementary Metal–Oxide–Semiconductor Operational Transconductance Amplifiers (OTAs): A Design Tutorial

This paper presents a comprehensive design tutorial for four types of single-stage operational transconductance amplifiers (OTAs): (1) five-transistor OTAs, (2) telescopic cascode OTAs, (3) folded cascode OTAs, and (4) current mirror OTAs. These OTAs serve as fundamental building blocks in analog circuits. The operational principles of each OTA are reviewed, and the key performance metrics are derived through a hand analysis. These performance metrics encompass most crucial parameters, including small-signal parameters, frequency response, input and output swing ranges, rising and falling slew rates, nonidealities, and bias circuit simplicity. All of these metrics are verified and compared using the simulation. Furthermore, the practical applications of each OTA are summarized, and a case study demonstrates the enhancement of a neural recording amplifier’s performance through appropriate OTA selection. A thorough review of the essential building blocks will become a stepping stone to design high-performance analog amplifiers across diverse applications.

Implementation of OTA in 90nm Technology with Bandgap Reference Application

Operational Transconductance Amplifier (OTA) is the basic building block of Analog circuit with linear input/output characteristics. Because it associates closely linked parameters like noise and settling performance, the current design methodologies for two-stage OTAs frequently result in sub-optimal solutions. The study discusses the implementation of an Operational transconductance amplifier (OTA) with a bandgap reference (BGR) circuit and its importance in providing a stable and accurate reference voltage for various analog and digital circuits. The combination of OTA and BGR provides a stable and accurate reference voltage that can be used in various analog and digital circuits. OTAs are used to drive high capacitive loads. To scale the dimensions of Complementary Metal Oxide Semiconductor (CMOS) technology requires proportional scaling, also taking supply voltage into consideration. In addition to the simplicity and strong performance that the Band Gap Reference (BGR) achieves as a load for the OTA circuit, the architecture of OTA with BGR as load is easily adaptable to attain high accuracy. Because the performance of the used amplifier has a significant impact on the OTA’s performance, consideration must be given to the design and its architecture. Therefore, it is essential to carry out a comparison analysis in order to get the optimal results of the outputs of OTA having BGR as the load.

GNN-Based Hierarchical Annotation for Analog Circuits

Analog designs consist of multiple hierarchical functional blocks. Each block can be built using one of several design topologies, where the choice of topology is based on circuit performance requirements. A major challenge in automating analog design is in the identification of these functional blocks, which enables the creation of hierarchical netlist representations. This can facilitate a variety of design automation tasks such as circuit layout optimization because the layout is dictated by constraints at each level, such as symmetry requirements, that depend on the topology of the hierarchical block. Traditional graph-based methods find it hard to automatically identify the large number of structural variants of each block. To overcome this limitation, this paper leverages recent advances in graph neural networks (GNNs). A variety of GNN strategies is used to identify netlist elements for circuit functional blocks at higher levels of the design hierarchy, where numerous design variants are possible. At lower levels of hierarchy, where the degrees of freedom in circuit topology are limited, structures are identified using graph-based algorithms. The proposed hierarchical recognition scheme enables the identification of layout constraints such as symmetry and matching, which enable high-quality hierarchical layouts. This method is scalable across a wide range of analog designs. An experimental evaluation shows a high degree of accuracy over a wide range of analog designs, identifying functional blocks such as low-noise amplifiers, operational transconductance amplifiers, mixers, oscillators, and band-pass filters in larger circuits.

Design of High Performance Operational Transconductance Amplifier

Designing high-performance analog circuits is becoming increasingly challenging with the persistent trend toward reduced supply voltages. The main bottleneck in an analog circuit is the operational amplifier. At large supply voltages, there is a trade off among speed, power, and gain, amongs to ther performance parameters. Often these parameters present contradictory choices for the op-amp architecture. At reduced supply voltages, output swing becomes yet another performance metric to be considered when designing the opamp. Of the several architecture folded cascode OTA is used in which all the transistors are in saturation regime. Furthermore, in an effort to reduce costs and integrate analog and digital circuits onto a single chip, the analog designer must often face the challenges using CMOS processes. This paper covers the design and implementation of a novel CMOS folded cascode OTA designed in 1m technology. Covered topic include current source and sinks, differential amplifier, compensation techniques, two stage compensated OTA and cascode OTA. Our design emphasis is on practical design where power consumption and speed are critical. The OTA has very low settling time and can be used for high speed applications, such Analog-to–Digital converters, high speed Sigma-delta ADC.

Operational Transconductance Amplifier Designed with Experimental Omega-Gate Nanowire SOI MOSFETs

The nanowire omega-gate technology is one of the possible technologies to replace the FinFET one in the semiconductor chip market. The omega-gate nanowire SOI MOSFET is considered a triple plus gate device, near the gate-all-around performance (figure 1) [1]. Due to the omega gate structure this device presents a better gate to channel electrostatic coupling than the FinFET devices, resulting in a greater immunity to short channel effects [1,2].The Operational Transconductance Amplifier (OTA) is a frequently used analog block in the integrated circuits. The studied OTA consists in a two-stage amplifier, where the first stage is a differential amplifier with active load and the second one is a common source amplifier, as can be seen in figure 2. This analog block is biased through the current source and the bias current is mirrored for each stage. In addition, negative feedback is used between the first and second stages with a compensation capacitor (miller capacitor) in order to stabilize the amplifier response.In this work, an OTA circuit is designed with SOI omega-gate nanowire experimental transistors. In order to find the best device to be used in the project, some measurements were carried out of several nanowire devices with different channel lengths (ranging from 20 nm to 200 nm). The schematic structure of the measured devices is presented in figure 3 [2]. Basic device parameters such as: transconductance (gm), output conductance (gd), Early voltage (VEA), threshold voltage (VT), transistor efficiency (gm/ID) and subthreshold slope (SS) were analyzed.The model of the experimental omega-gate transistors was performed using the Look Up Table (LUT) method. The capacitance measurements of the nanowire transistor were also considered, to simulate the frequency responses more faithfully. The simulator used to design the OTA circuit was Cadence using the Verilog-A language. It was obtained the main figure of merit of this block like voltage gain (Av), gain-bandwidth product (GBW), phase margin and power.A transistor efficiency (gm/ID) near 8 V-1 was chosen in order to compare the performance of OTA designed with omega-gate nanowire devices (NW-OTA) of this work with anothers OTAs designed with triple gate FinFETs (FinFET-OTA) and with nanosheets (NS-OTA) from the literature (Table 1) [3,4].Table 1 shows that the phase margin is close to 60o in all cases, ensuring the stability of the circuit. The NW-OTA presents higher voltage gain compared to FinFET-OTA due to the better gate to channel coupling. The NS-OTA presents the highest voltage gain of all cases, but it is the more expensive technology [4]. When GBW is analyzed for all 3 designs, the NW-OTA shows better results than the NS-OTA, using the same load capacitance of 200fF, thanks to the lower miller capacitance (Cc) required to keep the frequency behavior. The FinFET-OTA shows the best result in relation to GBW, but the FinFET-OTA project doesn’t consider a load capacitance, making the comparison unfair [3].Figure 4 shows the gain and phase of the OTA using a SOI omega-gate nanowire transistors.In summary, the OTA designed with SOI omega-gate nanowire technology presents a better performance than FinFET one, can be implemented in a smaller area on the chip (smaller Cc capacitor and smaller number of fins in parallel) and it is a cheaper option compared to nanosheet one. Figure 1

A Low-Power Capacitorless LDO Regulator with Transient Enhancement Structure

In this paper, a portable low-power low dropout regulator (LDO) with no output capacitance has been designed in 0.18-[Formula: see text]m CMOS technology. In this paper, a PMOS power transistor is used and combined with an overshoot and undershoot suppression circuit to improve the transient response of the circuit. A modified Class-AB operational transconductance amplifier (OTA) is used to reduce power consumption and act as an error amplifier to eliminate low frequency poles. At the same time, a super source follower and a Miller capacitor are used for frequency compensation of the system. Finally, the system can provide a stable voltage for a load step from 0.2 to 25[Formula: see text]mA in 500[Formula: see text]ns edge-time for 140[Formula: see text]pF-load capacitance. The test results show that the circuit achieves a good voltage regulation rate and high transient response.

A Power-Efficient Linearized Open-Loop OTA Utilizing Reconfigurable Tail-Resistor Pair

This brief presents a power-efficient open-loop operational transconductance amplifier (OTA) topology for sensing applications. Reconfigurable tail-resistor (RTR) technology is proposed to achieve exceptional odd-order harmonic distortion while maintaining excellent energy-efficiency to meet the different application needs of sensors. The key to achieving this performance is the reconfigurability of resistors based on switches and the degeneration of resistors for the exponentiation of transistors in sub-threshold region. Fabricated in a 180-nm CMOS technology, the prototype linearized OTA achieves -82-dB third harmonic suppression for an input signal of 100-mVin-diff employing the pseudo-differential degeneration configuration, and exhibits -77.6-dB linearity in the commonmode degeneration topology. And it only dissipates 3.6-lW from 1.35-V/1.8-V supply.

Miller compensated three-stage OTA for a wide range of load capacitors (1 pF to 1 nF)

ABSTRACT In this work, the miller with a feed-forward capacitor compensated three-stage Operational Transconductance Amplifier (OTA) for a wide range of load capacitors is presented. The proposed OTA can drive a load capacitor with a phase margin of more than from a smaller load capacitor of to a larger load capacitor of . It is difficult to stabilise multi-stage OTA for a wide range of load capacitors. The OTA needs a good compensator to stabilise the OTA. The proposed compensator uses a miller capacitor along with the small feed-forward capacitor to stabilise the three-stage OTA for a wide range of load capacitors. Usually, the miller compensated multi-stage OTA with more than two stages is unstable for the smaller load capacitors and demands a minimum load capacitor for the OTA to be stable, but the proposed OTA is stable even for a very small load capacitor of . The proposed structure uses a slew-rate enhancer (SRE) to enhance the transient performance of the OTA along with the feed-forward transconductors and achieves a settling time of over the wide range of load capacitors.

Resistorless Floating/Grounded Memristor Emulator Model With Electronic Tunability

The realization of memristor devices with specific operating parameters is a challenging task, which drives innovation in emulation circuits. This article offers a simple and novel resistorless memristor emulator design with an electronic controllability feature. The proposed model is suitable for both floating and grounded memristor applications and can operate in incremental/decremental modes effectively without switches. The proposed model comprises a voltage differencing current conveyor (VDCC) and an operational transconductance amplifier (OTA) as active components and requires a single capacitor as its passive element. This model emulates the memristors pinched hysteresis loop in current-voltage (I-V) plane. Simulation is carried out for a 180 nm CMOS technology with a supply voltage of 10.9 V. The proposed design exhibits non-linear behavior for a wide range of input voltage and operates well up to 8 MHz. The reliability and robustness of the proposed design have been verified for short-term non-volatility, temperature variation, Monte-Carlo and process corner analysis. The experimental verifications are carried out on a breadboard using ICs AD844 and CA3080.