Open-loop Voltage Gain Research Articles

0.35 V Subthreshold Bulk-Driven CMOS Second-Generation Current Conveyor

This study describes a high-performance second-generation Current Conveyor (CCII) operating at 0.35 V and achieving rail-to-rail operation at the Y terminal and class AB current drive at the X and Z terminals. The solution utilizes a low-voltage subthreshold bulk-driven CMOS OTA that was experimentally developed earlier, making systematic use of body terminals to improve small-signal and large-signal performance. The circuit has a high open-loop voltage gain and uses cascoded current mirror topologies, resulting in precise voltage and current transfer with bandwidths of 1.33 MHz and 2.13 MHz, respectively. The CCII offers a linear current drive up to 2.5 µA while consuming a total quiescent current of 2.86 µA (758 nA in the output branches), displaying one the highest figures of merit in terms of current utilization for sub 1 V solutions.

Using iMTGSPICE to Optimize Cascaded Miller OTAs and Boost Electrical Performance, Robustness and Reduce Die Area

Analog designers usually cascade several basic analog building blocks that were previously optimized to increase the open-loop voltage gain (AV0) and to avoid the increasing of the Design and Optimization Cycle Time (DOCT) of a given System-On-a-Chip. However, still exist a big doubt about if this approach is really better than that considering the implementation of amplifiers in cascade, without considering previously optimized analog building blocks. Thus, the main objective of this paper is to perform a detailed comparative study between robust amplifiers in cascade implemented without using analog building blocks previously designed and optimized and a similar one that uses analog building blocks previously designed and optimized (typical design approach). The computational design and optimization tool, named iMTGSPICE, which uses heuristics algorithms of the Artificial Intelligence integrated to the expertise of the analog designers (Human Intelligence), is used to perform these implementations to remarkably reduce DOCT of these implementations. This work demonstrates that it is possible to reduce the total gate area (44.6%) and to increase the operating temperature range from 0oC to 36oC to -40oC to 125oC of the robust amplifier in cascade that was implemented without using analog building blocks previously designed and optimized compared to one that was implemented by using analog building blocks previously designed and optimized.

Second Generation of Layout Styles to Further Boosting the Electrical Performance and Reducing the Die Area of Analog MOSFETs

Previous studies have been showing that the first generation of layout styles composed by the Diamond (hexagonal), Octo (octagonal) and Ellipsoidal gate shapes for implementing of the planar and three-dimensional MOSFETs are is capable of boosting their analog and digital electrical performances and also by reducing used die areas, when we replace conventional Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), that present rectangular gate shape, by those implemented by these innovative layout styles. In order to further boosting these features obtained by the use of first generation of layout styles, we are introducing one of elements of the second generation of layout styles for MOSFETs, intitled Half-Diamond. This new proposal is an evolution of Diamond layout style, in which it is able to preserve the Longitudinal Corner Effect (LCE), the Parallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and the Deactivation of Parasitic MOSFETs in Bird’s Beaks Regions (DEMPAMBBRE) effects of the first generation and also of further reducing the dimensions of conventional MOSFETs (CM) in which the Diamond MOSFETs have gotten to do. Thus, this work performs an experimental comparative study between the electric performances of MOSFETs implemented with the Half-Diamond, Diamond and Conventional layout styles, regarding the analog Complementary MOS (CMOS) integrated circuits (ICs) applications, which their channel lengths are not usually designed with the minimum dimension (Lmin) allowed by the CMOS ICs manufacturing processes. The results obtained show that, for instance, the saturation drain current normalized by the aspect ratio and low-frequency open-loop voltage gain, in dB, of MOSFET implemented with the Half-Diamond layout style (HDM) are 17% and 3.5% higher, respectively, than those found in CM counterparts. Besides, by using Half-Diamond layout style, it is possible of further reducing the die areas of analog CM and consequently of the analog CMOS ICs applications, in comparison to those reached by the use of Diamond layout styles, regarding a 180 nm Bulk CMOS ICs technology node.

A 50 dB high-gain operational amplifier integrated with metal-oxide TFTs

This paper presents a 50 dB high-gain operational amplifier (OPAMP), which is fabricated by unipolar n-type indium–zinc–oxide thin-film transistors. Different positive feedback technologies are employed to achieve sufficient voltage gain. The fabricated OPAMP exhibits an open-loop voltage gain (A v) of 50 dB over a −3 dB bandwidth of 15 kHz at the supply voltage of 20 V. The measured unity-gain frequency (f UG) and the DC power consumption are 500 kHz and 8.07 mW, respectively. In addition, an effective frequency compensation scheme is also introduced and simulated. The simulation results that the proposed OPAMP has a voltage gain of 50 dB with 60° phase margin at 150 kHz unity-gain frequency after compensation.

An ultra-low-power bulk-driven subthreshold super class-AB rail-to-rail CMOS OTA with enhanced small and large signal performance suitable for large capacitive loads

This paper introduces a power-efficient super class-AB bulk-driven (BD) operational transconductance amplifier (OTA) in the subthreshold region suitable for driving a high capacitive load. An improved auxiliary differential amplifier is employed using a cross-coupled connection to the gate of the input core differential pairs and its adaptive biasing BD FVF differential pairs to boost the input core transconductance and slew rate in superclass-AB mode. The utilization of a partial positive feedback operation further improves the open-loop voltage gain, overall effective transconductance, and unity-gain frequency (UGF) with a sufficient phase margin of 93⁰. The Post layout simulation results of the proposed OTA in Cadence DFW-II platform using UMC 0.18 μm technology for a 0.5 V single supply and a capacitive load of 200 pF confirm enhancement of 22 times slew rate, 54.32 dB DC gain, and 75 times UGF achieved by the proposed design over its conventional counterpart with only a narrow increase of 1.19 times in power expenditure.

A Common Drain Operational Amplifier Using Positive Feedback Integrated by Metal-Oxide TFTs

This paper presents a common-drain-based operational amplifier (OPAMP) fabricated by mono n-type indium-zinc-oxide (IZO) thin-film transistors (TFTs). Positive feedback technology is employed to the load TFTs by cross-coupled connection in order to boost the voltage gain of the common-drain differential pair. The OPAMP exhibits an open-loop voltage gain (Av) of 27 dB over a −3 dB bandwidth (BW) of 8.4 kHz at a DC supply voltage of 10 V. The measured unity-gain frequency (UGF), phase margin (PM) and DC power consumption are 119.4 kHz, 36° and 0.96 mW, respectively. Moreover, the chip area of the proposed OPAMP is as small as 0.37 mm $\times0.3$ mm since this concise topology needs only 10 TFTs.

Charge-Based Continuous Equations for the Transconductance and Output Conductance of Graded-Channel SOI MOSFET’s

This paper presents charge-based continuous equations for the transconductance and output conductance of submicrometer Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFET. The effects of carrier velocity saturation, channel length modulation and drain-induced barrier lowering were taken into account in the proposed equations. Experimental results were used to test the validity of the equations by comparing not only the transconductance and the output conductance, but also the Early voltage and the open-loop voltage gain, showing a good agreement in a wide range of bias.

Subthreshold biased enhanced bulk-driven double recycling current mirror OTA

This paper presents a single-stage bulk-driven double recycling low-voltage low-power operational transconductance amplifier (OTA) operating in subthreshold region. The proposed OTA utilizes double recycling topology and provides enough open loop voltage gain, slew rate, and unity gain frequency (UGF). The flipped voltage follower-based adaptively biased input differential pair working in class AB mode has ensured dynamic current boosting and increased slew rate. Further, the proposed OTA has utilized partial positive feedback to mitigate some of the performance reduction caused by the bulk-driven topology. The simulation results of the proposed OTA have ensured open loop gain of 79.5 dB, UGF of 37.1 kHz, and phase margin of 64°. It operates with dual power supply of ± 0.25 V and consumes low power of 60 nW. These performance parameters validate its usefulness for LV, LP and low-frequency applications. The process, voltage, and temperature variation effects on low-frequency voltage gain, UGF, and phase margin of the proposed OTA has also been investigated with process corner simulations. The proposed OTA is designed and simulated in UMC 180 nm standard n-tub bulk CMOS process technology utilizing Tanner EDA tools.

Analog design with Line-TFET device experimental data: from device to circuit level

This work studies the use of line-tunnel field effect transistor (Line TFET) devices in analog applications. It presents the DC and small signal characteristics of these devices and compares them with other TFET topologies and with conventional MOSFET technology. The Line-TFET’s saturation characteristics are also closely studied, through simulations and experimental characterization, revealing that point tunneling leakage from source to drain not only limits the bias voltage and the gate area but also makes the output conductance independent of the gate length. A common source stage is designed to illustrate and further explore this fact, making comparisons with conventional MOSFET technology. In order to obtain an amplifier with very high voltage gain, a two-stage operational transconductance amplifier is designed considering two different starting points: fixed transistor efficiency (gm/Ids) or fixed normalized current (Ids/W) in order to obtain similar conditions of performance for Line-TFET and MOSFET devices. It is revealed that the Line-TFET design always achieves much higher intrinsic voltage gain (of up to 115 dB) and is more suitable for low power, low frequency applications. Thus, a third design is performed with Line-TFET devices by using gate lengths of 100 nm, achieving 71 dB of open loop voltage gain and 18 nW of power dissipation, which may be suitable for applications such as bio-signal acquisition.

Using the Octagonal Layout Style to Implement the Pass MOSFET to Improve the Electrical Performance of the CL–LDO Voltage Regulator

This paper presents a study by SPICE simulations and experimental data of a capacitor-less low-dropout (CL–LDO) voltage regulator (VR) by using a novel backend technique to improve its electrical performance. This study regards the use of an octagonal layout style in the pass device MOSFET of a CL–LDO VR to mainly boost its open-loop voltage gain and reduce output impedance. The results show that this innovative layout approach used in the CL–LDO voltage regulator can increase its power supply rejection ratio (PSRR) in approximately 2 dB (60 Hz), without degrading its quiescent current (Iq) (improvement of 2% better), and without wasting additional die area, in comparison to the one that its pass MOSFETs was implemented by using standard rectangular layout style. The 130 nm Bipolar Complementary Metal-Oxide-Semiconductor (BiCMOS) manufacturing process from GlobalFoundries was used to implement both CL–LDO VRs, via MOSIS Educational Program. The die areas of each CL–LDO VRs are the same and equal to 0.00994mm2.

Bulk-driven class AB fully-balanced differential difference amplifier

This paper presents a new low-voltage class AB fully-balanced differential difference amplifier (FB-DDA) employing the bulk-driven technique. At the FB-DDA differential pairs the bulk terminal of the MOS transistors are used as signal inputs in order to increase the common-mode input range under low supply voltage. At the class AB output stages the bulk terminal of the MOS transistors are used as control inputs in order to adjust the quiescent currents and compensate them against the process and temperatures (P/T) variation. The voltage supply of the FB-DDA is 0.7 V and the quiescent power consumption is 8.3 µW. The open loop voltage gain is 68 dB and the gain–bandwidth product is 168 kHz for 10 pF capacitive load. The circuit performance was simulated in Cadence/Spectre environment using the TSMC 0.18 µm CMOS process.

CdS Thin Film Transistor for Inverter and Operational Amplifier Circuit Applications

Organic and inorganic thin film transistors (TFTs) are fabricated, simulated, and tested for circuit applications. The devices are based on polycrystalline cadmium sulfide (CdS) and pentacene thin films. Both devices are simulated and analyzed using two-dimensional finite element simulation methodology. For CdS, grain boundary and uniform trap distribution approaches are implemented. It is assumed that traps due to grain boundaries are uniformly distributed throughout the film. For pentacene a Poole–Frenkel mobility model is employed. After matching device simulation with experimental data, the SPICE model parameters are extracted for circuit simulation. The devices are tested for both analog and digital circuits. operational amplifier (OPAMP) and inverter circuits are tested. Two OPAMP topologies are compared and the results are discussed. One of the topologies is based on all n-type transistors using CdS TFT and the other topology is the two-stage Miller compensated CMOS design based on CdS and pentacene TFTs. The operational amplifiers have an open-loop voltage gain of 25.9dB and 29.7dB respectively. The performance of the CMOS design is found to be limited by performance of pentacene transistor.

An HEMT-Based Cryogenic Charge Amplifier for Sub-kelvin Semiconductor Radiation Detectors

We present the design and noise performance of a fully cryogenic ( $$T=4$$ K) high-electron mobility transistor (HEMT)-based charge amplifier for readout of sub-kelvin semiconductor radiation detectors. The amplifier is being developed for use in direct detection dark matter searches such as the cryogenic dark matter search and will allow these experiments to probe weakly interacting massive particle masses below 10 GeV/ $$c^2$$ while retaining background discrimination. The amplifier dissipates $$\approx $$ 1 mW of power and provides an open loop voltage gain of several hundreds. The measured noise performance is better than that of JFET-based charge amplifiers and is dominated by the noise of the input HEMT. An optimal filter calculation using the measured closed loop noise and typical detector characteristics predicts a charge resolution of $$\sigma _q$$ =106 eV (35 electrons) for leakage currents below $$4 \times 10^{-15}$$ A.

0.4-V bulk-driven differential-difference amplifier

A new solution for an ultra-low-voltage, low-power, bulk-driven fully differential-difference amplifier (FDDA) is presented in the paper. Simulated performance of the overall FDDA for a 50nm CMOS process and supply voltage of 0.4V, shows dissipation power of 31.8μW, the open loop voltage gain of 58.6dB and the gain-bandwidth product (GBW) of 2.3MHz for a 20pF load capacitance. Despite the very low supply voltage, the FDDA exhibits rail-to-rail input/output swing. The circuit performance has also been tested in two applications; the differential voltage follower and the second-order band-pass filter, showing satisfactory accuracy and dynamic range.

IGZO TFT-Based All-Enhancement Operational Amplifier Bent to a Radius of 5 mm

An all-enhancement operational amplifier operating at 5 V and comprising 16 n-type amorphous indium-gallium-zinc-oxide thin-film transistors (TFTs) is fabricated on a 50 μm thick flexible polyimide substrate. The operational amplifier has an open loop voltage gain of 18.7 dB and a unity-gain frequency of 472 kHz while the common-mode rejection ratio (CMMR) is larger than 40 dB. The mechanical flexibility of the amplifier is demonstrated by bending the circuit to a radius of 5 mm, which corresponds to a tensile strain of 0.5% parallel to the TFT channels. The bent amplifier shows the same output behavior as when flat. The power consumption of the operational amplifier is 900 μW, regardless whether the circuit is flat or bent.

Design of a Low-Voltage Low-Power CMOS Operational Amplifier

A low voltage, low power two-stage operational amplifier (op-amp) was proposed in this paper. A folded-cascode structure is used in the input stage of the amplifier to get high gain. Current mirrors are used in the input stage to make the transconduotance constant. A simple push-pull common source amplifier is adopted as the output stage to take the advantages of its high efficiency. The experimental results show that the unity-gain bandwidth is 12.5MHz, the low-frequency open-loop voltage gain is 100dB,the phase margin is 65°, and power dissipation is 98.8μw.

A CMOS OTA with extremely large DC open-loop voltage gain

A CMOS OTA with extremely large DC open-loop voltage gain

Nonclassical Channel Design in MOSFETs for Improving OTA Gain-Bandwidth Trade-Off

In this paper, gain-bandwidth (GB) trade-off associated with analog device/circuit design due to conflicting requirements for enhancing gain and cutoff frequency is examined. It is demonstrated that the use of a nonclassical source/drain (S/D) profile (also known as underlap channel) can alleviate the GB trade-off associated with analog design. Operational transconductance amplifier (OTA) with 60 nm underlap S/D MOSFETs achieve 15 dB higher open loop voltage gain (AVO_OTA) along with three times higher cutoff frequency (fT_OTA) as compared to OTA with classical nonunderlap S/D regions. Underlap design provides a methodology for scaling analog devices into the sub-100 nm regime and is advantageous for high temperature applications with OTA, preserving functionality up to 540 K. Advantages of underlap architecture over graded channel (GC) or laterally asymmetric channel (LAC) design in terms of GB behavior are demonstrated. Impact of transistor structural parameters on the performance of OTA is also analyzed. Results show that underlap OTAs designed with spacer-to-straggle (s/ σ) ratio of 3.2 and operated below a bias current (IBIAS) of 80 μA demonstrate optimum performance. The present work provides new opportunities for realizing future ultra wide band OTA design with underlap DG MOSFETs in silicon-on-insulator (SOI) technology.

Harmonic Distortion of Unstrained and Strained FinFETs Operating in Saturation

The harmonic distortion (HD) exhibited by unstrained and biaxially strained fin-shaped field-effect transistors operating in saturation as single-transistor amplifiers has been investigated for devices with different channel lengths L and fin widths Wfin. The study has been performed through device characterization, 3-D device simulations, and modeling. Nonlinearity has been evaluated in terms of second- and third-order HDs (HD2 and HD3, respectively), and a discussion on its physical sources has been carried out. Also, the influence of the open-loop voltage gain AV in HD has been observed.

Simulation of OTA's with Double-Gate Graded-Channel MOSFETS using the Symmetric Doped Double-Gate Model

In this paper, Operational Transconductance Amplifiers (OTA's) were simulated in SPICE using the Symmetric Doped Double-Gate Model which includes the capacitances of Double-Gate (DG) transistors. In this work, all the transistors have been simulated using just one model for lightly doped transistors (TLD), high doped transistors (THd) N-channel devices and P-channel devices. These OTA's show an improvement in the high open-loop voltage gain which is related mainly to the reduction of the drain output conductance which gives higher Early voltages for DG GC transistors.