Abstract
This paper presents a common-drain-based operational amplifier (OPAMP) fabricated by mono n-type indium-zinc-oxide (IZO) thin-film transistors (TFTs). Positive feedback technology is employed to the load TFTs by cross-coupled connection in order to boost the voltage gain of the common-drain differential pair. The OPAMP exhibits an open-loop voltage gain (Av) of 27 dB over a −3 dB bandwidth (BW) of 8.4 kHz at a DC supply voltage of 10 V. The measured unity-gain frequency (UGF), phase margin (PM) and DC power consumption are 119.4 kHz, 36° and 0.96 mW, respectively. Moreover, the chip area of the proposed OPAMP is as small as 0.37 mm $\times0.3$ mm since this concise topology needs only 10 TFTs.
Highlights
IN large-area and flexible electronics, thin-film transistors (TFTs) technology plays an important role in the integration for analog and digital building blocks
It is worthy to mention that, combining both merits of low temperature polycrystalline silicon (LTPS) TFTs with high on-current and oxide TFTs with low off-current, a CMOS operational amplifier (OPAMP) with excellent performance is successfully realized by low temperature polycrystalline silicon oxide (LTPO) technology in [19]
NMOS-only OPAMP design using metaloxide TFTs is constrained by the absence of available PMOS transistors for integration, thereby a current source load with high output resistance due to poor device mobility [20]
Summary
Abstract—This paper presents a common-drain-based operational amplifier (OPAMP) fabricated by mono n-type indium-zinc-oxide (IZO) thin-film transistors (TFTs). Positive feedback technology is employed to the load TFTs by cross-coupled connection in order to boost the voltage gain of the common-drain differential pair. The OPAMP exhibits an openloop voltage gain (Av) of 27 dB over a -3 dB bandwidth (BW) of 8.4 kHz at a DC supply voltage of 10 V. The measured unity-gain frequency (UGF), phase margin (PM) and DC power consumption are 119.4 kHz, 36° and 0.96 mW, respectively. The chip area of the proposed OPAMP is as small as 0.37 mm × 0.3 mm since this concise topology needs only 10 TFTs
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