Open-base Breakdown Voltage Research Articles

High-Gain Gated Lateral Power Bipolar Junction Transistor

We demonstrated a prototype Gated Lateral power bipolar junction transistor (GLP-BJT) on wide bandgap semiconductor. The device combined the intrinsic advantages of high current gain of a Gated Lateral-BJT and good current handling and voltage blocking capabilities of GaN material. As a result, the common-emitter current gain remained over 300 at a high collector current density of 2 kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> despite a wide p-base region of 2 μm. The open base breakdown voltage BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CEO</sub> was over 300 V corresponding to a high critical field of 2.5 MV/cm. These figures of merit show great promise of GaN-based GLP-BJT in power applications and also shed light on the development of state-of-the-art bipolar transistors based on other wide bandgap semiconductors.

(Invited) High-Performance GaN Hbts with Regrown Emitters

GaN-based hetero-junction bipolar transistors (HBTs) are suitable for power amplifiers because they have inherent advantages such as high current and power density, high linearity and normally off operation. However, low conductivity in the p-type base layer and plasma-induced dry-etching damage slow down the improvement of GaN HBTs. Although GaN-based HBTs demonstrated large current gain (β) and high current and power density by using p-type InGaN base [1], N2-incorporation dry-etching process, wet repairing and regrown base contact layer [2,3], etching damage also exists, which limits the maximum oscillation frequency (fmax) [4]. This essay reports an AlGaN/GaN heterojunction bipolar transistor (HBT) on sapphire with selective-area regrown (SAG) n-AlGaN emitter by metal-organic chemical vapor deposition (MOCVD). 1-μm n+-GaN, 0.5-μm undoped-GaN and 100-nm p-GaN are grown on sapphire in sequence by MOCVD. Then a 100-nm thick SiO2 mask layer is deposited on the wafer and patterned for SAG emitter. Then the wafer is reloaded to reactor to grow an n-AlGaN emitter layer at 980 ℃ and 50 torr. Hall measurements performed on p-GaN base layer indicate a hole concentration of 9.8×1017 /cm3 and mobility of 14.1 cm2/V.s. The SAG n-AlGaN emitter is 100-nm thick with the Al component of 7%. The electron concentration and mobility of the SAG n-AlGaN layer are 1.6×1018 /cm3 and 290 cm2/V s. Ohmic contact is achieved on the base contact with the calculated sheet resistance Rs of 238 KΩ/sq, and the specific contact resistance ρc of 2×10-3 Ω.cm2. As a result, the fabricated HBTs exhibit high β of 110, which is highest among reported values on GaN-based HBTs on sapphire substrates. The common-emitter I-V characteristics show a high J C of 22 kA/cm2 and power density of 220 kW/cm2 with a low Voffset <1V and Vknee<5V. These voltage are the lowest among reported values on GaN-based HBTs with comparable emitter areas, owing to the realization of base ohmic contact that decreases base resistance. The open-base breakdown voltage is 98 V with the leakage current of 1 μA, as a consequence the breakdown field is about 2.2 MV/cm. we also demonstrated RF performance of GaN HBTs with fT of 4 GHz at the collector voltage of 9 V, although the chip size is large. It is expected that high RF performance can be achieved by down scaling the device layout. These results for GaN HBTs/sapphire show that high performance III-N HBTs can be achieved with regrowth technology. In this talk, we will demonstrate that a large performance improvement can be obtained for RF HBT devices by the use of regrowth emitter. The current gain is increased with the emitter area decreasing. It is favorable for RF HBT devices, which are expected to achieve higher current gain, benefiting from small recombination current. By down scaling the device layout, an RF HBT is expected to be used in PA in the next generation communication.

AlGaN/GaN Heterojunction Bipolar Transistor With Selective-Area Grown Emitter and Improved Base Contact

We report AlGaN/GaN n-p-n heterojunction bipolar transistors (HBTs) on sapphire substrates with selective-area grown AlGaN emitters by metal–organic chemical vapor deposition. Metal–semiconductor contact on the external p-GaN base layer shows ohmic characteristics thanks to the dry-etching-free process of base–emitter junction. As a result, the maximum current gain $\beta $ is around 90 calculated from the Gummel plot of a ${20}\times {20}\,\,\mu \text{m}^{{2}}$ HBT device. Common-emitter ${I}$ – ${V}$ family curves exhibit offset voltage $({V} _{\text {offset}}) V and knee voltage $({V} _{\text {knee}}) V. A high current density $ {J}_{\text C}$ of 8 kA/cm2 and power density of 75 kW/cm2 were obtained. These values are the highest in the reported for GaN-based HBTs on sapphire substrates. The open-base breakdown voltage ( ${BV}_{\text {CEO}}$ ) exceeds 98 V comparable with direct-growth GaN-based HBTs.

Silicon carbide bipolar junction transistor with novel emitter field plate design for high current gain and reliability

A silicon carbide bipolar junction transistor with novel emitter field plate (EFP-BJT) design is proposed in this paper. The fabricated EFP-BJT features a metal plate of the extending emitter electrode with a 50-nanometer-thick oxide layer overlapped on the extrinsic base surface. The contrast of experimental results show that a 56% increase of maximum current gain is obtained by the EFP-BJT compared with a conventional SiC BJT (C-BJT), with the EFP-BJT’s current gain of 43 measured at the collector current density (JC) of 716 A cm−2 corresponding to a specific on-state resistance (RSP_ON) of 5.4 mΩ · cm2 and open-base breakdown voltage (BVCEO) of 1.5 kV. The novel EFP-BJTs are entirely compatible with the process and design considerations of the conventional ones. The in-depth mechanism comparisons between the proposed EFP-BJT and C-BJT are studied by the simulation tool TCAD Silvaco. The surface recombination effect of EFP-BJT is greatly reduced by the modulation of the emitter field plate. Additionally, due to the surface recombination suppression of the novel structure, EFP-BJTs have effectively enhanced reliability. Compared with C-BJTs, there is no significant degradation of the collector current for the fabricated EFP-BJTs under the forward current stress test.

4H-SiC monolithic Darlington transistors with slight current gain drop at high collector current density

Profit from high current gain features, 4H-SiC power Darlington transistor has the capacity for handling high current transmission. In this paper, monolithic Darlington transistors were fabricated using a simultaneous formation process for both n-type (emitter) and p-type (base) ohmic contact. The isolated device shows current gain of 1061 and 823 with collector current density ( J C) increasing from 200 to 800 A/cm2, exhibiting a slight current gain drop at high J C. By extracting the interface state density ( D it) between SiO2 and p-type 4H-SiC, it is found that this advantage owes to the improvement of the shallow bulk minority carrier lifetime in base region. Furthermore, ISE-TCAD (technology computer aided design) simulation was carried out to study the relationship between base minority lifetime and the current gain, from which the total base minority lifetime is estimated to be 48 ns. The open base breakdown voltage ( BV CEO) is 850 V at a leakage current of 2 μA due to the electric filed crowding at the isolation bottom between drive bipolar junction transistor (BJT) and output BJT. To solve this, non-isolated devices were also fabricated with improved BV CEO of 2370 V, indicating the superior potential of 4H-SiC monolithic Darlington transistors for high power application, while the current gain is deceased to 420, which needs further improvement.

500 °C High Current 4H-SiC Lateral BJTs for High-Temperature Integrated Circuits

High-current 4H-SiC lateral BJTs for high-temperature monolithic integrated circuits are fabricated. The BJTs have three different sizes and the designs are optimized in terms of emitter finger width and length and the device layout to have higher current density (JC), lower on-resistance (RON), and more uniform current distribution. A maximum current gain ( $\beta $ ) of >53 at significantly high current density was achieved for different sizes of SiC BJTs. The BJTs are measured from room temperature to 500 °C. An open-base breakdown voltage (VCEO) of >50 V is measured for the devices.

Impact of Lateral Scaling on Silicon Germanium High Breakdown Power Amplifier Device Performance

Silicon Germanium (SiGe) Heterojunction Bipolar Transistors (HBTs) in Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) technologies have in recent years, emerged as a viable alternative to Gallium Arsenide (GaAs) [1] for commercial development of linear power amplifier (PA) modules for wireless communications. The explosion in WLAN applications at 2.4GHz has provided ample opportunity for SiGe BiCMOS to substantially penetrate the PA market [2]. SiGe HBTs offer several benefits compared to it’s GaAs HBT counterparts including the ability to provide high integration at a reduced cost [3]. The higher thermal conductivity associated with the silicon substrate enables reduced chip areas, smaller packages and provides improvements in chip robustness. Additionally, SiGe BiCMOS integration facilitates improved power densities, on-chip matching and bias chokes, temperature compensated power detector and a CMOS compatible interface [2]. SiGe HBT PA device design limits have traditionally been constrained by the performance tradeoff described by the Johnson limit, which states that the product of the current gain, fT and the DC open-base breakdown voltage, BVceo, should be relatively constant[3]. However, it is now generally accepted that DC emitter-open breakdown voltage, BVcbo is a more useful indicator of device ruggedness for PA applications. This arises since SiGe HBT operation in PA applications have been demonstrated at voltages significantly higher than BVceo, [1,4]. Furthermore, power-gain cut-off frequency, fMAX , has also been cited as relevant a device metric for PAs as fT , [1,3] and several authors have suggested that improvements in fMAX will enhance PA device performance. Typically, improvements in device fMAX are achieved by lateral scaling to accomplish a reduction in the base resistance and collector-base capacitance. Since SiGe HBT device physics do not demand rigid tradeoff between BVcbo and fMAX, , several potential device optimization opportunities exist for PA applications. Technology computer-aided design (TCAD) has been used to optimize the PA design performance relative to the base technology. The TCAD methodology was based on a detailed strategy which entailed developing a process and device model calibration for an existing 0.35um SiGe HBT device that features non-self-aligned emitter-base integration, with a carbon doped SiGe base layer and an implanted extrinsic base region [2]. The model calibration featured a close match of both process and electrical characteristics to the measured data. An important element to matching the electrical characteristics of the device, was simulating key artifacts of the process related to epitaxial growth of the SiGe base layer, which defined the final device topology. The calibration served as the baseline simulation for the optimization study and provided insight into the device performance limitations. The simulations demonstrated the device breakdown, BVcbo, occurs along the extrinsic region of the collector and the base, and is correspondingly set by the thickness of the collector n-epitaxial layer and the vertical diffusion of the extrinsic base into the collector. Several lateral scaling strategies were therefore investigated, which addressed optimization of collector-base capacitance, Ccb and base resistance, Rb for improvements in fMAX and BVcbo. Scaling the lateral dimension of the device resulted in improvements in the performance metrics peak fT , peak Ic and fMAX . Improvements in fT and Ic are explained by the reduced surface field effect, whereby a more uniform field distribution delays base push out effect in the transistor[5]. The AC and DC characteristcs will be reviewed.

Improvement of High-Frequency Characteristics of InGaAsSb-Base Double Heterojunction Bipolar Transistors by Inserting a Highly Doped GaAsSb Base Contact Layer

This letter presents InP/GaAsSb/InGaAsSb/InP double heterojunction bipolar transistors (DHBTs) with a highly doped base contact layer. In order to reduce the base contact resistivity, a 3-nm-thick highly doped GaAsSb contact layer is inserted between the InP emitter and 17-nm-thick composition- and doping-graded InGaAsSb base. Fabricated DHBTs with a 0.25-μm emitter show a current gain of 32 and a high open-base breakdown voltage BVCEO of 5.2 V. The DHBTs also exhibit fT/f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> = 513/637 GHz at a collector current density of 9.5 mA/μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and VCE = 1 V. The f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> is higher by 124 GHz than that for InP/InGaAsSb DHBTs without the GaAsSb contact layer. These results indicate that the use of the GaAsSb/InGaAsSb base structure is very effective in improving f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> .

Improvement of Current Gain and Breakdown Voltage in 4H-SiC BJTs Employing High-k Dielectric as an Interfacial Layer

This paper proposes a new structure of 4H-SiC bipolar junction transistor, which can both achieve high current gain and high open base breakdown voltage. By introducing a groove type of metal-high k dielectric-silicon carbide (MIS) structure into the active region along the base-emitter sidewall which is formed with the process of isolation etching, a large electric field appears at the interface between high-k dielectric and bulk material by analyzing the potential distribution in forward mode, thus accelerating the electron transport. Based on a doping concentration of 4×1017cm-3 and thickness of 0.6um base region, current gain of as high as 191 is obtained using TCAD simulation, and that is almost double of the conventional structure in the same simulation setup. Furthermore, a field plate structure is composed combined with the base contact metal simultaneously, and the open base breakdown voltage is obviously increased from 634V to 948V with a 6μm-thick n-SiC collector (Nd=3×1015cm-3).

5.8-kV Implantation-Free 4H-SiC BJT With Multiple-Shallow-Trench Junction Termination Extension

Implantation-free 4H-SiC bipolar junction transistors with multiple-shallow-trench junction termination extension have been fabricated. The maximum current gain of 40 at a current density of 370 A/ $\mathrm{cm}^{2}$ is obtained for the device with an active area of 0.065 $\mathrm{mm}^{2}$ . A maximum open-base breakdown voltage (BV) of 5.85 kV is measured, which is 93% of the theoretical BV. A specific on-resistance ( $R_{\mathrm{{\scriptstyle ON}}}$ ) of 28 m $\Omega \cdot {\rm cm^{2}}$ was obtained.

An InGaAs/InP DHBT With Simultaneous $\text{f}_{\boldsymbol \tau }/\text{f}_{\text {max}}~404/901$ GHz and 4.3 V Breakdown Voltage

We report an InP/InGaAs/InP double heterojunction bipolar transistor fabricated in a triple-mesa structure, exhibiting simultaneous 404 GHz f τ and 901 GHz f max . The emitter and base contacts were defined by electron beam lithography with better than 10 nm resolution and smaller than 20 nm alignment error. The base-collector junction has been passivated by depositing a SiN x layer prior to benzocyclobutene planarization, improving the open-base breakdown voltage BV CEO from 3.7 to 4.3 V.

(Invited) Combining SiGe BiCMOS and InP Processing in an on-top of Chip Integration Approach

Applications such as radar imaging and wideband communications are driving the research on millimeter-wave circuits. For some applications SiGe hetero junction bipolar transistors (HBTs) are limited in output power. III-V technologies (like InP) can realize devices showing a high product of peak transit frequency multiplied with the open base breakdown voltage. Therefore, merging the qualities of both III-V and Si technology will enable a new class of high-performance ICs. Our approach combines an InP-DHBT transferred-substrate process with a Si-BiCMOS process. The key method is an aligned face-to-face wafer bonding with a subsequent removal of the InP substrate. Different integrated signal sources with an output frequency up to 246 GHz were designed and produced using different combinations of BiCMOS and InP circuit building blocks to demonstrate the capabilities of the hetero-integration routine. In this paper the influences of the wafer bonding and the finalization of the InP-DHBT process on SiGe devices were investigated. It was found that the influences on the BiCMOS devices were rather small.

(Invited) Reliability of SiGe HBTs in Long-Term Operation

Introduction In the ongoing development towards RF circuits with still higher operation frequencies SiGe HBT technologies continuously have to prove their competitiveness against advanced Si CMOS and compound semiconductor millimeter-wave circuits. Yet, besides excellent RF performance at circuit operation frequencies – meanwhile even well beyond 100 GHz –customer focus is also put on operating constraints (“safe operating area”, SOA) and long-term reliability of the devices.If the HBT power load in a circuit stays within the SOA limits but collector voltage surpasses open-base breakdown voltage (BVCEO) or the emitter-base (EB) diode is reverse biased a gradual decrease of the HBT current gain (“beta ageing”) can usually be observed (Fig. 1a). This beta degradation is correlated to an increase of the base recombination current caused by recombination centers (“traps”) at dielectric interfaces. These again are being created by hot carrier injection (“HCI”).This interface trap generation and the gradual character of ageing are in contrast with device failure of III-V devices where defects are generated inside the semiconductor and failure shows more abrupt and end-of-life characteristics [1].Concerning HBT reliability the questions to address then are: What is the maximum HBT beta degradation tolerable for any specific circuit operation? Will it stay within this limit during the anticipated circuit life-time (up to 20 years for space applications)? Our intention therefore was to develop an ageing function which describes base current change or beta degradation, respectively, as function of electrical stressors, ambient temperature, and stress time. The experimental setups to evaluate ageing are forward and reverse bias stress conditions which we applied for up to 1000h and in a temperature range from -40°C up to 150°C. Operation Constraints The SOA to which device operation should be restricted can be derived from the common-base output characteristics which indicate device instabilities by current pinch-in or electro-thermal runaway. For low-voltages electro-migration will define maximum current densities. The latter can to be avoided be defining proper design guidelines for the metal line layout. Interface Defect Generation and Annihilation Even within SOA sufficiently high electrical fields in the collector-base (CB) space charge region will trigger avalanche carrier multiplication there and part of them will be accelerated towards EB and CB spacer oxides interfaces (HCI). Subsequently, interface traps will be created by de-passivation of Si dangling bonds. Trap density is expected to evolve as Nit ~ tα with α ≈ 0.25 [2] as long as the reaction is far from saturation (i.e. trap density becomes comparable to the total areal density of interface dangling bonds). Contrary, thermal activated hydrogen re-passivation of traps leads to beta recovery. Electrical Stress and Annealing Tests Currently, two types of electrical stress tests have been established as basis for SiGe HBT reliability evaluation:Forward “mixed-mode” (MM) stress with applied VCB,stress > BVCEO and forced emitter current density JE,stress up to a few times the value corresponding to peak-fT,“REV” stress with reverse biased BE junction. Additionally, to study defect annealing we applied a combination of high current and VCB,stress > BVCEO at ambient temperatures up to 150°C to achieve junction temperatures well above 200°C. Figure 1a shows as an example the impact of 100 h REV stress and subsequent anneal on a HBT with 250 GHz peak-fT from IHP’s 0.13 µm BiCMOS technology [3]. At VBE = 0.7 V over 90% beta reduction can be observed during reverse stress (2) but annealing with junction temperature reaching 300°C lead to almost complete beta recovery (3). Ageing Function The additional trap recombination saturation currents have been evaluated as function of the relevant stressors [4]IBEr,MM = f(VCB,stress, IE,stress, Tambient)·tα IBEr,REV = f(VEB,stress, Tambient)·tα and can be added to the according compact model base current. Figure 1b shows for example base current increase as function of VEB,stressafter 100h of REV stress. This ageing function can be used to predict HBT ageing and its impact on circuit performance during circuit life cycle.

InP/InGaAs/InP DHBT structures with high carbon-doped base grown by gas source molecular beam epitaxy

A new InP/InGaAs/InP DHBT structure with high carbon (C)-doped base was optimized and grown successfully by gas source molecular beam epitaxy (GSMBE) in this work. The C-doping concentration is 3×1019cm−3 with carrier mobility of 66.3cm2/Vs. Characteristics of C-doped InGaAs materials were investigated. High quality InP/InGaAs/InP DHBT structural materials were obtained. The InP/InGaAs/InP DHBT device with emitter area of 100×100μm2 was fabricated. The open base breakdown voltage (VBCEO) of 4.2V and current gain of 60 at VCE of 3.0V were achieved. All these results prove the material is suitable for DHBT device fabrication.

Fabrication and characterization of 4H—SiC bipolar junction transistor with double base epilayer

In this paper we report on a novel structure of a 4H—SiC bipolar junction transistor with a double base epilayer that is continuously grown. The measured dc common-emitter current gain is 16.8 at IC = 28.6 mA (JC = 183.4 A/cm2), and it increases with the collector current density increasing. The specific on-state resistance (Rsp−on) is 32.3 mΩ·cm2 and the open-base breakdown voltage reaches 410 V. The emitter N-type specific contact resistance and N+ emitter layer sheet resistance are 1.7×10−3 Ω·cm2 and 150 Ω/□, respectively.

Arsenic-doped Ge-spiked monoemitter SiGe:C heterojunction bipolar transistors by low-temperature trisilane based chemical vapor deposition

In this work we optimized the Ge-spiked monoemitter for the SiGe:C heterojunction bipolar transistor by using low-temperature trisilane based chemical vapor deposition to meet the requirements of high growth rate and high electrically-active doping levels of arsenic. The resultant devices show improvement of open-base breakdown voltage and no degradation of cutoff frequency with incorporation of a Ge spike in the monoemitter.

High Voltage, Low On-Resistance 4H-SiC BJTs with Improved Junction Termination Extension

In this work, implantation-free 4H-SiC bipolar transistors with two-zone etched-JTE and improved surface passivation are fabricated. This design provides a stable open-base breakdown voltage of 2.8 kV which is about 75% of the parallel plane breakdown voltage. The small area devices shows a maximum dc current gain of 55 at Ic=0.33 A (JC=825 A/cm2) and VCESAT = 1.05 V at Ic = 0.107 A that corresponds to a low ON-resistance of 4 mΩ•cm2. The large area device shows a maximum dc current gain of 52 at Ic = 9.36 A (JC=312 A/cm2) and VCESAT = 1.14 V at Ic = 5 A that corresponds to an ON-resistance of 6.8 mΩ•cm2. Also these devices demonstrate a negative temperature coefficient of the current gain (β=26 at 200°C) and positive temperature coefficient of the ON-resistance (RON = 10.2 mΩ•cm2).

High Current-Gain Implantation-Free 4H-SiC Monolithic Darlington Transistor

An implantation-free 4H-SiC Darlington transistor with high current gain of 2900 (J <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> = 970 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE</sub> = 6 V) at room temperature is reported. The device demonstrates a record maximum current gain of 640 at 200°C, offering an attractive solution for high-temperature applications. The monolithic Darlington device exhibits an open-base breakdown voltage of 1 kV that is less than the optimum bulk breakdown due to isolation trench between the driver and the output bipolar junction transistor. On the same wafer, a monolithic Darlington pair with a nonisolated base layer was also fabricated. At room temperature, this device shows a maximum current gain of 1000 and an open-base breakdown voltage of 2.8 kV, which is 75% of the parallel-plane breakdown voltage.

Avalanche multiplication and pinch-in models for simulating electrical instability effects in SiGe HBTs

The onset of impact ionization-induced instabilities limits the operative range of SiGe hetero-junction bipolar transistors. Based on referential Monte Carlo simulation results, a critical review of major models for the avalanche multiplication factor (M) is presented, and a new analytical model is proposed and successfully verified by measurements. The novel M formulation has been incorporated in a two-dimensional theoretical model describing bipolar transistor operation under pinch-in conditions/above the open-base breakdown voltage BV CEO. The physical mechanisms leading to electrical instability are addressed, and closed form analytical relations defining the onset of instability under forced-I E conditions are derived. The proposed model defines the limits of the Safe Operating Area (SOA) related to impact ionization, enabling the reliable usage of HBTs above BV CEO.

10 kV, 10 A Bipolar Junction Transistors and Darlington Transistors on 4H-SiC

4H-SiC Bipolar Junction Transistors (BJTs) and hybrid Darlington Transistors with 10 kV/10 A capability have been demonstrated for the first time. The SiC BJT (chip size: 0.75 cm2 with an active area of 0.336 cm2) conducts a collector current of 10 A (~ 30 A/cm2) with a forward voltage drop of 4.0 V (forced current gain βforced: 20) corresponding to a specific on-resistance of ~ 130 mΩ•cm2 at 25°C. The DC current gain, β, at a collector voltage of 15 V is measured to be 28 at a base current of 1 A. Both open emitter breakdown voltage (BVCBO) and open base breakdown voltage (BVCEO) of ~10 kV have been achieved. The 10 kV SiC Darlington transistor pair consists of a 10 A SiC BJT as the output device and a 1 A SiC BJT as the driver. The forward voltage drop of 4.5 V is measured at 10 A of collector current. The DC forced current gain at the collector voltage of 5.0 V was measured to be 440 at room temperature.