Impact of Lateral Scaling on Silicon Germanium High Breakdown Power Amplifier Device Performance

Abstract

Silicon Germanium (SiGe) Heterojunction Bipolar Transistors (HBTs) in Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) technologies have in recent years, emerged as a viable alternative to Gallium Arsenide (GaAs) [1] for commercial development of linear power amplifier (PA) modules for wireless communications. The explosion in WLAN applications at 2.4GHz has provided ample opportunity for SiGe BiCMOS to substantially penetrate the PA market [2]. SiGe HBTs offer several benefits compared to it’s GaAs HBT counterparts including the ability to provide high integration at a reduced cost [3]. The higher thermal conductivity associated with the silicon substrate enables reduced chip areas, smaller packages and provides improvements in chip robustness. Additionally, SiGe BiCMOS integration facilitates improved power densities, on-chip matching and bias chokes, temperature compensated power detector and a CMOS compatible interface [2]. SiGe HBT PA device design limits have traditionally been constrained by the performance tradeoff described by the Johnson limit, which states that the product of the current gain, fT and the DC open-base breakdown voltage, BVceo, should be relatively constant[3]. However, it is now generally accepted that DC emitter-open breakdown voltage, BVcbo is a more useful indicator of device ruggedness for PA applications. This arises since SiGe HBT operation in PA applications have been demonstrated at voltages significantly higher than BVceo, [1,4]. Furthermore, power-gain cut-off frequency, fMAX , has also been cited as relevant a device metric for PAs as fT , [1,3] and several authors have suggested that improvements in fMAX will enhance PA device performance. Typically, improvements in device fMAX are achieved by lateral scaling to accomplish a reduction in the base resistance and collector-base capacitance. Since SiGe HBT device physics do not demand rigid tradeoff between BVcbo and fMAX, , several potential device optimization opportunities exist for PA applications. Technology computer-aided design (TCAD) has been used to optimize the PA design performance relative to the base technology. The TCAD methodology was based on a detailed strategy which entailed developing a process and device model calibration for an existing 0.35um SiGe HBT device that features non-self-aligned emitter-base integration, with a carbon doped SiGe base layer and an implanted extrinsic base region [2]. The model calibration featured a close match of both process and electrical characteristics to the measured data. An important element to matching the electrical characteristics of the device, was simulating key artifacts of the process related to epitaxial growth of the SiGe base layer, which defined the final device topology. The calibration served as the baseline simulation for the optimization study and provided insight into the device performance limitations. The simulations demonstrated the device breakdown, BVcbo, occurs along the extrinsic region of the collector and the base, and is correspondingly set by the thickness of the collector n-epitaxial layer and the vertical diffusion of the extrinsic base into the collector. Several lateral scaling strategies were therefore investigated, which addressed optimization of collector-base capacitance, Ccb and base resistance, Rb for improvements in fMAX and BVcbo. Scaling the lateral dimension of the device resulted in improvements in the performance metrics peak fT , peak Ic and fMAX . Improvements in fT and Ic are explained by the reduced surface field effect, whereby a more uniform field distribution delays base push out effect in the transistor[5]. The AC and DC characteristcs will be reviewed.