On-state Current Research Articles

AlN/Si 기판 상에 성장된 바나듐 이산화물 박막 기반 전자 소자에서 광열 효과로 제어되는 고반복률 전류 스위칭

In this study, an electronic device based on a vanadium dioxide (VO₂) heterostructure thin film grown on an aluminum nitride(AlN)/silicon(Si) substrate was fabricated to realize high-repetition-rate current switching controlled by the photothermal effect. In the conventional VO₂/sapphire(Al₂O₃) device, the current switching controlled by the photothermal effect takes a long time for the cooling process to return the device to the off-state. This problem made high-repetition-rate switching impossible. On the other hand, it was assumed that the VO₂/AlN/Si device would be suitable for high-repetition-rate switching because it has a higher critical temperature and superior thermal conductivity than the VO₂/Al₂O₃ device. And, we demonstrated the photothermally-controlled current switching with a repetition rate of up to 60㎐ while maintaining a high on-state current of 50㎃ using an optimized experimental setup and anewly fabricated device. The switching response time was also improved to 1ms level.

Improvements in 2D p-type WSe2 transistors towards ultimate CMOS scaling

This paper provides comprehensive experimental analysis relating to improvements in the two-dimensional (2D) p-type metal–oxide–semiconductor (PMOS) field effect transistors (FETs) by pure van der Waals (vdW) contacts on few-layer tungsten diselenide (WSe2) with high-k metal gate (HKMG) stacks. Our analysis shows that standard metallization techniques (e.g., e-beam evaporation at moderate pressure ~ 10–5 torr) results in significant Fermi-level pinning, but Schottky barrier heights (SBH) remain small (< 100 meV) when using high work function metals (e.g., Pt or Pd). Temperature-dependent analysis uncovers a more dominant contribution to contact resistance from the channel access region and confirms significant improvement through less damaging metallization techniques (i.e., reduced scattering) combined with strongly scaled HKMG stacks (enhanced carrier density). A clean contact/channel interface is achieved through high-vacuum evaporation and temperature-controlled stepped deposition providing large improvements in contact resistance. Our study reports low contact resistance of 5.7 kΩ-µm, with on-state currents of ~ 97 µA/µm and subthreshold swing of ~ 140 mV/dec in FETs with channel lengths of 400 nm. Furthermore, theoretical analysis using a Landauer transport ballistic model for WSe2 SB-FETs elucidates the prospects of nanoscale 2D PMOS FETs indicating high-performance (excellent on-state current vs subthreshold swing benchmarks) towards the ultimate CMOS scaling limit.

Aligned Carbon Nanotube Arrays with Germanium Protective Layers for Improving the Performance of Radio Frequency Transistors

Aligned carbon nanotube arrays with high semiconducting purity and high density have been regarded as an ideal channel material for constructing high-frequency field effect transistors and high-speed integrated circuits. However, contaminants (mainly resist residues) that leave the surface of carbon nanotubes during the fabrication process seriously deteriorate the interface contact quality, which will trigger large contact resistance and thus inhibit the ultimate performance of the carbon nanotube-based transistors. Here, we demonstrate a germanium protective layer technique that can keep a clean surface of carbon nanotube films from the contaminants during device fabrication and thus boost the quality of ohmic contact between carbon nanotubes (CNTs) and metal. The transfer length method (TLM) is used to evaluate the effect of the germanium protective layer technique on the ohmic contact resistance. The contact resistance from metal–CNTs extracted using the TLM was reduced by 93%, from 1.66 to 0.123 KΩ μm before and after the germanium process treatment. Owing to the great improvement of contact between metal and CNTs by introducing the germanium protective layer technique, the fabricated aligned CNT array-based radio-frequency field-effect transistors with a gate length of 110 nm on the quartz substrate present excellent DC performance, with an on-state current of 1.28 mA/μm and maximum transconductance of up to 1.05 mS/μm at a bias of −1.2 V. Meanwhile, the as-measured current gain cut-off frequency (fT,EXT) and power gain frequency (fMAX,EXT) increase from 12 to 110 GHz and 13 to 105 GHz, respectively. This approach provides a simple and reproducible means of improving the interface quality and reducing contact resistance in CNT-based devices to enhance performance.

Rhombohedral-stacked bilayer transition metal dichalcogenides for high-performance atomically thin CMOS devices.

Van der Waals coupling with different stacking configurations is emerging as a powerful method to tune the optical and electronic properties of atomically thin two-dimensional materials. Here, we investigate 3R-stacked transition-metal dichalcogenides as a possible option for high-performance atomically thin field-effect transistors (FETs). We report that the effective mobility of 3R bilayer WS2 (WSe2) is 65% (50%) higher than that of 2H WS2 (WSe2). The 3R bilayer WS2 n-type FET exhibits a high on-state current of 480 μA/μm at Vds=1 V and an ultralow on-state resistance of 1 kilohm·μm. Our observations, together with multiscale simulations, reveal that these improvements originate from the strong interlayer coupling in the 3R stacking, which is reflected in a higher conductance compared to the 2H stacking. Our method provides a general and scalable route toward advanced channel materials in future electronic devices for ultimate scaling, especially for complementary metal oxide semiconductor applications.

Study of ambipolar and linearity behavior of the misaligned double gate-drain dopant-free Nano-TFET: Design and performance enhancement

Work done in this article demonstrates the charge plasma based misaligned double gate-drain doping less tunnel field effect transistor. Designed devices such as perfectly aligned and misaligned, both are optimized by considering the secondary drain in order to investigate ambipolar and linearity behavior. As the work function of secondary drain increases reduction in the ambipolar current is observed with a little degradation in ON state current. It presents a tradeoff between ambipolar current and ON current hence suitable work function of secondary drain is necessary for the proper working of the device. Analog parameters such as ON current, ambipolar current, subthreshold slope, ON to OFF current ratio, ON current to ambipolar current ratio, threshold voltage are analyzed with respect to secondary drain. In order to investigate the device performance for low voltage and low noise applications various linearity parameters such as higher order transconductances, higher order harmonic distortions, higher order intermodulation point and transconductance gain factor have also been demonstrated all the designed structures. The values of ON current for perfectly aligned, underlap, overlap and both gate misaligned structure at 4.2eV of secondary drain work function is 52 μA, 30 μA, 18 μA and 12 μA respectively. And ambipolar current for perfectly aligned, underlap, overlap and both gate misaligned structure at 4.2eV of secondary drain work function is 3 pA, 23 pA, 247 pA and 705 pA respectively.

Ambipolar performance improvement of the C-shaped pocket TFET with dual metal gate and gate–drain underlap

Dual-metal gate and gate–drain underlap designs are introduced to reduce the ambipolar current of the device based on the C-shaped pocket TFET(CSP-TFET). The effects of gate work function and gate–drain underlap length on the DC characteristics and analog/RF performance of CSP-TFET devices, such as the on-state current (I on), ambipolar current (I amb), transconductance (g m), cut-off frequency (f T) and gain–bandwidth product (GBP), are analyzed and compared in this work. Also, a combination of both the dual-metal gate and gate–drain underlap designs has been proposed for the C-shaped pocket dual metal underlap TFET (CSP-DMUN-TFET), which contains a C-shaped pocket area that significantly increases the on-state current of the device; this combination design substantially reduces the ambipolar current. The results show that the CSP-DMUN-TFET demonstrates an excellent performance, including high I on (9.03 × 10−9 A/μm), high I on/I off (∼1011), low SSavg (∼13 mV/dec), and low I amb (2.15 × 10−2 A/μm). The CSP-DMUN-TFET has the capability to fully suppress ambipolar currents while maintaining high on-state currents, making it a potential replacement in the next generation of semiconductor devices.

Simulation of a Steep-Slope p- and n-Type HfS2/MoTe2 Field-Effect Transistor with the Hybrid Transport Mechanism

The use of a two-dimensional (2D) van der Waals (vdW) metal-semiconductor (MS) heterojunction as an efficient cold source (CS) has recently been proposed as a promising approach in the development of steep-slope field-effect transistors (FETs). In addition to the selection of source materials with linearly decreasing density-of-states-energy relations (D(E)s), in this study, we further verified, by means of a computer simulation, that a 2D semiconductor-semiconductor combination could also be used as an efficient CS. As a test case, a HfS2/MoTe2 FET was studied. It was found that MoTe2 can be spontaneously p-type-doped by interfacing with n-doped HfS2, resulting in a truncated decaying hot-carrier density with an increasing p-type channel barrier. Compared to the conventional MoTe2 FET, the subthreshold swing (SS) of the HfS2/MoTe2 FET can be significantly reduced to below 60 mV/decade, and the on-state current can be greatly enhanced by more than two orders of magnitude. It was found that there exists a hybrid transport mechanism involving the cold injection and the tunneling effect in such a p- and n-type HfS2/MoTe2 FET, which provides a new design insight into future low-power and high-performance 2D electronics from a physical point of view.

Ultrashort channel chemical vapor deposited bilayer WS2 field-effect transistors

Two-dimensional transition metal dichalcogenides (TMDs) are potential candidates for next generation channel materials owing to their atomically thin structure and high carrier mobility, which allow for the ultimate scaling of nanoelectronics. However, TMDs-based field-effect transistors are still far from delivering the expected performance, which is mainly attributed to their high contact resistance and low saturation velocity (vsat). In this work, we report high-performance short-channel WS2 transistors based on bandgap engineering. The bilayer WS2 channel not only shows a higher average field-effect mobility (μFE) than the monolayer channel but also exhibits excellent metal-Ohmic contact using a regular physical vapor deposition deposited Ni/Au contact, reducing the Rc value to a record low value of 0.38 kΩ · μm without any intentional doping. The bilayer WS2 device of the 80 nm channel exhibits a high on-state current of 346 μA/μm at Vds = 1 V, near-zero drain-induced barrier lowering, and a record high Ion/Ioff ratio over 109. Furthermore, a record high on-state current of 635 μA/μm at Vds = 1 V and a record high vsat of 3.8 × 106 cm/s have been achieved for a shorter 18 nm channel device, much higher than previous WS2 transistors. This work reveals the intrinsically robust nature of bilayer WS2 crystals with promising potential for integration with conventional fabrication processes.

Controlling Drain Side Tunneling Barrier Width in Electrically Doped PNPN Tunnel FET

In this paper, we propose and investigate an electrically doped (ED) PNPN tunnel field effect transistor (FET), in which the drain side tunneling barrier width is effectively controlled to obtain a suppressed ambipolar current. We present that the proposed PNPN tunnel FETs can be realized without chemically doped junctions by applying the polarity bias concept to a doped N+/P- starting structure. Using numerical device simulations, we demonstrate how the tunneling barrier width on the drain side can be influenced by several design parameters, such as the gap length between the channel and the drain (Lgap), the working function of the polarity gate, and the dielectric material of the spacer. The simulation results show that an ED PNPN tunneling FET with an ED drain, which has been explored for the first time, exhibits a low ambipolar current of 5.87 × 10-16 A/µm at a gap length of 20 nm. The ambipolar current is reduced by six orders of magnitude compared to that which occurs with a conventional ED PNPN tunnel FET with a uniformly doped drain, while the average subthreshold slope and the ON state and OFF state currents remained nearly identical.

Approaching the quantum limit in two-dimensional semiconductor contacts.

The development of next-generation electronics requires scaling of channel material thickness down to the two-dimensional limit while maintaining ultralow contact resistance1,2. Transition-metal dichalcogenides can sustain transistor scaling to the end of roadmap, but despite a myriad of efforts, the device performance remains contact-limited3-12. In particular, the contact resistance has not surpassed that of covalently bonded metal-semiconductor junctions owing to the intrinsic van der Waals gap, and the best contact technologies are facing stability issues3,7. Here we push the electrical contact of monolayer molybdenum disulfide close to the quantum limit by hybridization of energy bands with semi-metallic antimony ([Formula: see text]) through strong van der Waals interactions. The contacts exhibit a low contact resistance of 42 ohm micrometres and excellent stability at 125 degrees Celsius. Owing to improved contacts, short-channel molybdenum disulfide transistors show current saturation under one-volt drain bias with an on-state current of 1.23 milliamperes per micrometre, an on/off ratio over 108 and an intrinsic delay of 74 femtoseconds. These performances outperformed equivalent silicon complementary metal-oxide-semiconductor technologies and satisfied the 2028 roadmap target. We further fabricate large-area device arrays and demonstrate lowvariability in contact resistance, threshold voltage, subthreshold swing, on/off ratio, on-state current and transconductance13. The excellent electrical performance, stability and variability make antimony ([Formula: see text]) a promising contact technology for transition-metal-dichalcogenide-based electronics beyond silicon.

Sub-9 nm high-performance and low-power transistors based on an in-plane NbSe2/MoSe2/NbSe2 heterojunction.

Due to the ability to reduce the gate length of field-effect transistors (FETs) down to sub-10 nm without obviously affecting the performance of the device, the utilization of two-dimensional (2D) semiconductor materials as channel materials for FETs is of great interest. However, in-plane 2D/2D heterojunction FETs have received less attention in previous studies than vertical van der Waals heterojunction devices. Based on the above reasons, this study has investigated the transport properties of an in-plane NbSe2/MoSe2/NbSe2 heterojunction FET with different gate lengths by using ab initio quantum transport simulation. The results reveal that a gate length of sub-9 nm gives the device a low subthreshold swing down to 62 mV dec-1 and a high on-state current up to 1040 μA μm-1. Most importantly, the on-state current, delay time, and power dissipation of the FET with the optimized channel length can nearly meet or even exceed the high-performance and low-power requirements of the International Technology Roadmap for Semiconductors. The findings for this FET can provide the design and development guidance for other in-plane heterojunction electrical devices in the post-Moore era.

Complementary Resistive Switching in ZnO/Al2O3 Bi-Layer Devices

This paper reports the complementary resistive switching (CRS) characteristics exhibited by Au/ZnO/Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /Fluorine doped tin oxide (FTO) bilayer device for the first time, where both ZnO and Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> are active switching layers exhibiting resistive switching properties. The I-V characteristics of the device initially show bipolar resistive switching (BRS) for a few cycles (∼12) before permanently switching to CRS with the extension of SET voltage. The stable CRS state of the device exhibits a high current of ∼500 μA during the ON-state and low current of 3x10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-7</sup> A during OFF-state at low input voltages (-0.5 V to 0.5V) enables the proposed device suitable to use in crossbar array to mitigate the sneak path current. The device performance to write and read processes is evaluated with pulses of magnitudes ∼|2.5| V and 1.3 V, respectively, and showed a ∼ 60μA difference in read-out current between data bits 0 and 1. Similarly, the device's power consumption is also measured to elucidate that the device is suitable to use as a memory unit with power consumption in the order of microwatts (μW). Further, the possible switching mechanism is demonstrated based on oxygen vacancies migration.

Исследование динамики включения низковольтных InP-гомотиристоров

A series of heterostructure designs of low-voltage InP homothyristors have been investigated using numerical simulation methods. The design with a space charge layer formed in the p-base region of the n-p-n transistor part was considered as the base one. The dynamic characteristics and processes that determine the rate of transition to the on state are investigated. It is shown that as the p-base thickness increases from 1 to 2.6 μm, the maximum on-state currents increase from 70 to 90 A, while the minimum turn-on transition time is 11 ns at a maximum blocking voltage of 55 V. It is shown that the operation efficiency in the on state is determined by the residual voltage. Residual voltage decreases with a decrease in the thickness of the p-base.

Modulated wafer-scale WS2 films based on atomic-layer-deposition for various device applications.

Tungsten disulfide (WS2) is promising for potential applications in transistors and gas sensors due to its high mobility and high adsorption of gas molecules onto edge sites. This work comprehensively studied the deposition temperature, growth mechanism, annealing conditions, and Nb doping of WS2 to prepare high-quality wafer-scale N- and P-type WS2 films by atomic layer deposition (ALD). It shows that the deposition and annealing temperature greatly influence the electronic properties and crystallinity of WS2, and insufficient annealing will seriously reduce the switch ratio and on-state current of the field effect transistors (FETs). Besides, the morphologies and carrier types of WS2 films can be controlled by adjusting the processes of ALD. The obtained WS2 films and the films with vertical structures were used to fabricate FETs and gas sensors, respectively. Among them, the Ion/Ioff ratio of N- and P-type WS2 FETs is 105 and 102, respectively, and the response of N- and P-type gas sensors is 14% and 42% under 50 ppm NH3 at room temperature, respectively. We have successfully demonstrated a controllable ALD process to modify the morphology and doping behavior of WS2 films with various device functionalities based on acquisitive characteristics.

The effects of source doping concentration and doping gradient on the ON-state current of Si nanowire TFETs

The tunnel field-effect transistor (TFET) is considered a promising next-generation transistor due to its potentially limit-breaking low subthreshold swing and better immunity against short-channel effects. However, the low ON-state current (ION) of TFETs has been a critical problem. In this work, we investigated the effects of the source doping concentration and the source doping gradient (SDG) on the ION of n-type Si gate-all-around (GAA) nanowire (NW) TFETs using an ATLAS device simulator. Unexpectedly, we found that increasing the source doping concentration does not necessarily improve ION, especially for TFETs with a large SDG. Moreover, although reducing the SDG indeed increases ION, for TFETs with low source doping concentration (e.g., 1 × 1019 cm−3), the improvement in ION by reducing the SDG becomes insignificant.

Normally-OFF AlGaN/GaN-based HEMTs with decreasingly graded AlGaN cap layer

In this work, an enhancement-mode (E-mode) AlGaN/GaN-based high-electron-mobility transistor (HEMT) with a graded AlGaN cap layer (GACL) is proposed and numerically studied by Silvaco technology computer-aided design. The GACL is designed with a decreasingly graded Al composition x along [0001] direction and the initial x is smaller than the Al composition of the Al0.2Ga0.8N barrier layer (BL). This GACL scheme can simultaneously produce high-concentration polarization-induced holes and negative net polarization charges at the GACL/BL interface. This can facilitate the separation of the conduction band (E C) and Fermi level (E F) at the 2DEG channel and therefore benefit the normally-OFF operation of the device. The optimized graded-AlGaN-gated metal-semiconductor HEMT can achieve a large threshold voltage of 4 V. Furthermore, we demonstrated that shortening the gate length on the GACL and inserting an oxide layer between the gate and GACL can be both effective to suppress gate leakage current, enhance gate voltage swing, and improve on-state drain current of the device. These numerical investigations can provide insights into the physical mechanisms and structural innovations of the E-mode GaN-based HEMTs in the future.

Design optimization of a silicon-germanium heterojunction negative capacitance gate-all-around tunneling field effect transistor based on a simulation study

The steep sub-threshold swing of a tunneling field-effect transistor (TFET) makes it one of the best candidates for low-power nanometer devices. However, the low driving capability of TFETs prevents their application in integrated circuits. In this study, an innovative gate-all-around (GAA) TFET, which represents a negative capacitance GAA gate-to-source overlap TFET (NCGAA-SOL-TFET), is proposed to increase the driving current. The proposed NCGAA-SOL-TFET is developed based on technology computer-aided design (TCAD) simulations. The proposed structure can solve the problem of the insufficient driving capability of conventional TFETs and is suitable for sub-3-nm nodes. In addition, due to the negative capacitance effect, the surface potential of the channel can be amplified, thus enhancing the driving current. The gate-to-source overlap (SOL) technique is used for the first time in an NCGAA-TFET to increase the band-to-band tunneling rate and tunneling area at the silicon–germanium heterojunction. By optimizing the design of the proposed structure via adjusting the SOL length and the ferroelectric layer thickness, a sufficiently large on-state current of 17.20 μA can be achieved and the threshold voltage can be reduced to 0.31 V with a sub-threshold swing of 44.98 mV/decade. Finally, the proposed NCGAA-SOL-TFET can overcome the Boltzmann limit-related problem, achieving a driving current that is comparable to that of the traditional complementary metal–oxide semiconductor devices.

The Advantages and Applications of IGBT Compared with Conventional BJT and MOSFET

Nowadays, the power semiconductor devices have been used in many fields like wind power generation systems, the rail transit. Bipolar junction transistors (BJTs) and metal-oxide-semiconductor field-effect transistors (MOSFETs) as well as some other devices are the dominating the market. The insulated gate bipolar transistor (IGBT) as a mixed device of the BJT and the MOSFET, has a preeminent performance. In this paper, the characteristics of the punch through IGBT (PT-IGBT), the MOSFET and the BJT will be investigated by TCAD. Then the PT-IGBT is compared with the BJT and the MOSFET, for concluding its advantages. According to the simulation result, the PT-IGBT has the on-state current of 9*10-4A and the forward blocking voltage of 1200V, which are much higher than the other two devices. In the end of the paper, the development of the semiconductor devices is predicted, about the research trends.

Performance Limit of Gate-All-Around Si Nanowire Field-Effect Transistors: An Ab Initio Quantum Transport Simulation

The gate-all-around (GAA) $\mathrm{Si}$ nanowire (NW) field-effect transistor (FET) is considered one of the most promising successors of the current mainstream $\mathrm{Si}$ fin FET (FinFET) owing to its better electrostatic gate control. Experimentally, the diameter of $\mathrm{Si}$ NWs has been scaled down to 1 nm. In this paper, the performance limit of the GAA $\mathrm{Si}$ NWFET with a 1-nm diameter is investigated by utilizing ab initio quantum transport simulations. We prove that the electrical conduction is concentrated in the core of the ultranarrow wire channel. The minimum gate length (${L}_{g}$) at which the n- and p-type GAA $\mathrm{Si}$ NWFET can satisfy the high-performance application requirements (on-state current, gate capacitance, delay time, and power dissipation) of the International Technology Roadmap for Semiconductors is 3 nm. The best-performing 5-nm-${L}_{g}$ n-type GAA $\mathrm{Si}$ NWFET exhibits an energy-delay product comparable with typical monolayer two-dimensional FETs. Compared with the similar-sized trigate $\mathrm{Si}$ NW FinFET, an approximately 200% increase in the on-state current and about 15% decrease in the subthreshold swing are witnessed in GAA $\mathrm{Si}$ NWFET at the same 5-nm ${L}_{g}$. Through strain engineering, about an 80% increase of on-state current is observed in the 5-nm-${L}_{g}$ p-type GAA $\mathrm{Si}$ NWFET. Our research demonstrates the vast potential of the GAA $\mathrm{Si}$ NWFET in the sub-3-nm gate-length region.

Performance investigation and impact of trap charges on novel lateral dual gate oxide-bilateral tunnelling based field effect transistor

Tunnel field effect transistors (TFETs) offer advantage of robustness against short channel effects. However, reliability issues caused by interface trap charges (ITCs) generated during the fabrication in TFET is a major concern. Thus, in this manuscript, device reliability of proposed lateral dual gate oxide (DGO) bilateral tunnelling-based Tunnel FET (BT-TFET) has been examined for the first time. In this device, gate dielectric employs dual oxide, which enhances capacitive coupling between the gate and dielectric, thus, boosting various performance parameters of the device. Observation has been made that the proposed DGO BT-TFET exhibits enhanced ION/IOFF ratio of around 1012 and reduced subthreshold swing of 7.17 mV/decade against ION/IOFF ratio of around 107 and subthreshold swing of 17.82 mV/decade exhibited by the conventional device. Device reliability of the proposed device has been examined through a comparison of the effects of positive and negative trap charges on the DC, Analogue/RF attributes, for instance electric field, transfer characteristics, cut-off frequency (fT), etc. of the proposed DGO BT-TFET and traditional single gate oxide (SGO) BT-TFET. The study reveals that positive (negative) ITCs increase (decrease) the ON-state current, fT of DGO BT-TFET and SGO BT-TFET by 37.82 % (29.62 %), 25.07 % (28 %) and 538.57 % (99.99 %), 430.76 % (96.5 %) respectively. Besides, linearity distortion parameters for instance second order voltage intercept point (VIP2), third order transconductance coefficients etc. and transient analysis have also been studied and compared for both the devices. It turns out that positive (negative) interface traps enhance (reduce) VIP2 of DGO BT-TFET and SGO BT-TFET by 4.2 % (0.81 %) and 76.3 % (81.3 %), respectively. Thus, indicating that DGO BT-TFET has enhanced resistance in terms of performance variation when compared with SGO BT-TFET for various ITCs.