On-resistance Value Research Articles

An analog switch circuit structure suitable for low-distortion transmission

Abstract A MOSFET analog switch circuit structure suitable for low-distortion bidirectional signal transmission is proposed. By introducing a “threshold voltage matching MOSFET” into the MOSFET switch driver circuit structure, the driving voltage corrected by the threshold voltage is generated by the driving circuit, eliminating the problem of poor conduction on-resistance flatness in traditional analog switch circuit structure due to MOSFET second-order effects and non-constant overdrive voltage. The circuit completed schematic and layout design based on the 0.13 μm BCD process. Simulation results show that the switch has bidirectional transmission capability, with a typical on-resistance value of 115 Ω. It achieves less than 5% on-resistance non-flatness under resistive loads ranging from 500 Ω to 1 KΩ, which is more than 50% improvement compared to traditional analog switch structures. Moreover, the on-resistance flatness is insensitive to changes in load and temperature.

Ultra-low turn-on voltage quasi-vertical GaN Schottky barrier diode with homogeneous barrier height

Quasi-vertical Schottky Barrier Diodes (SBDs) with near to ideal turn-on voltage and ideality factor (n) of 1.02, were fabricated on a GaN on Si substrate. The average turn-on voltage and on-resistance values were found to be 0.23 ± 0.005 V (at 1 A/cm2) and 1.76 ± 0.11 mΩcm2, respectively with diode series resistance of 11 Ω. The analysis of the current–voltage curve revealed a temperature-independent barrier height, however the capacitance–voltage method showed a negative temperature coefficient. This discrepancy is discussed in the paper. Variable range hopping through dislocations is shown to be the dominant reverse current leakage mechanisms identified in the fabricated diode, with a characteristic temperature, T0 of 2 × 1010 K.

Novel Error-Tolerant Voltage-Divider-Based Through-Silicon-Via Test Architecture

A voltage-divider-based through-silicon-via (TSV) test architecture tests the TSV by using the voltage value differently divided according to TSV defects. This architecture is widely used for TSV testing owing to its small hardware overhead and high test speed. However, the existing voltage-divider-based TSV test architectures are vulnerable to process–voltage–temperature (PVT) variations and noise. In addition, they cannot effectively detect pinhole defects. This study proposes a novel error-tolerant voltage-divider-based TSV test architecture to address these problems. The proposed architecture reduces the test errors by appropriately adjusting the on-resistance value of each MOSFET and adding a compensator circuit. In addition, it effectively detects the pinhole defects by modifying the voltage divider structure and changing the MOSFET control method. Experimental results reveal that the proposed architecture promptly tests various TSV defects and significantly reduces the test errors.

Contact resistance in sub-micron and nanoscale organic thin-film transistors

Two improved methods for evaluating contact resistance in organic thin-film transistors (TFTs) are presented. These methods can be applied to TFTs with any arbitrary geometry and are also suitable for retroactive analysis of current-voltage characteristics. The first method is based on the analysis of the differential conductance of TFTs and in separating the conductivity contributions from the contacts and the channel. This method provides accurate results when the contact resistance is approximately 0.1–10 times the channel resistance. The second method is especially applicable to nanoscale and short channel length TFTs. The minimum value of differential on-resistance as a function of drain bias is used to separate the contributions of the channel and contact resistances at various drain voltages. This method is accurate when the contact resistance is approximately 0.3–10 times the channel resistance, as verified by simulations. It works even when there is no distinct saturation in current-voltage characteristics with increasing drain voltage. Both methods have been applied to experimental data from organic TFTs with channel lengths in the range 10 nm to 5 μm. • Two novel methods of extracting contact resistance in OTFTs are introduced. • Contact resistance of various channel lengths OTFTs are extracted and analyzed. • Effects of contact resistance in short channel pentacene TFTs are discussed. • New design of ultra-short channel TFTs is proposed to improve carrier injection.

Characterization of Threshold Voltage Instability Under Off-State Drain Stress and Its Impact on p-GaN HEMT Performance

The p-GaN gate technology is commonly implemented to achieve normally OFF gallium nitride (GaN) devices. Nonetheless, the threshold voltage instability under OFF-state stress remains a concern. In this article, the characterization technique of threshold voltage shift is proposed and the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift's impact on device performance is investigated. Specifically, a fast V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> the measurement circuit is introduced and validated to successfully characterize both the magnitude and the time-constant of the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift. According to the experimental results, the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> increases by more than 50% within several μs after the high drain voltage is applied. In contrast, the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> slowly (tens of seconds) gets back to the static value after the stress is removed. Following the characterization, the threshold voltage instability's impact on the device's static/switching performance is studied experimentally. A knee point shift is observed at low gate voltage, and the static ON-resistance value remains unchanged. Regarding the switching performance, the turn-ON loss increases by >20% after the high drain voltage stress. The change in turn-ON loss can be reduced when the gate resistance is decreased from 20 to 0 Ω. In terms of the turn-OFF loss, the impact of the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift is negligible. It is concluded that time-dependent threshold voltage shift needs to be considered in p-GaN device's modeling, and high gate drive voltage together with low gate resistance is recommended to mitigate the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> instability's effect on p-GaN high-electron-mobility transistor's performance.

Nonvolatile Analog Switch for Low-Voltage Applications

In this paper, a nonvolatile switch based on n-type floating-gate transistors is described. The switch states are programmed through the memory cell floating-gate voltage, allowing higher levels than the application supply. Furthermore, due to its nonvolatile nature, the power consumption is reduced. The on-state resistance, which does not depend on the supply voltage, is one of the greatest advantages of this type of switch in comparison to conventional switches. This benefit can be successfully exploited in low-voltage applications. The switch on-resistance can be increased without the need for increasing the switch area. The characteristics of the proposed switch were confirmed by the experimental results obtained on a test chip fabricated in a 0.18 µm EEPROM process. Measured on-resistance values between 45 and 70 Ω were obtained for a floating-gate voltage of 6.2 V and input source levels below 2 V. The required programming voltage was 18 V. The maximum off-state leakage current was measured at 5 nA.

Leakage Current Modelling and Optimization of β-Ga 2 O 3 Schottky Barrier Diode with Ni Contact under High Reverse Voltage

The reverse leakage current under high reverse voltage of a Ni/β-Ga 2 O 3 Schottky barrier diode (SBD) is numerically modelled and compared to measurements. universal Schottky tunnelling, thermionic emission and image-force lowering were taken into account. Furthermore, when type conversion under high reverse voltage has occurred at the top interface between Ni and β-Ga 2 O 3 and the SBD behaved as P–i–N diode, band to band tunnelling is proposed in association with the usually used Selberherr’s Impact ionization to model avalanche breakdown. The obtained breakdown voltage and specific on-resistance value are 434 V and 2.13 mΩ·cm2, respectively, fairly close to measurement values of 440 V and 2.79 mΩ·cm2. Optimization is performed based on the insertion of an intrinsic layer between Ni and the β-Ga 2 O 3 drift layer. It was found that 0.4 μm gave better Baliga’s figure of merit of 9.48107 W·cm−2 with breakdown voltage and specific on-resistance of 465 V and 2.28 mΩ·cm2, respectively. Finally, a surface edge termination design based on TiO2 insulator plate is adopted and the best obtained breakdown voltage, Baliga’s figure of merit and specific on-resistance were 1466 V, 1.98 × 109 W·cm−2 and 1.98 mΩ·cm2 respectively.

Short Circuit Ruggedness of 600 V SiC Trench JFETs

Silicon Carbide JFETs with low on-state resistance are suitable for a number of high power applications. The static, dynamic and short circuit characterization of 600 V SiC Trench JFETs are reported in this paper. Typical JFETs fabricated with a 1.2 μm cell pitch had an on-resistance value around 40 mΩ and blocking voltages of ~600 V across the wafer. JFETs were successfully switched with a dc link voltage of 300 V, a current of 15 A and operating temperature of 125 °C. These JFETs were subjected to a short circuit condition with duration ranging from 10 μs to 45 μs at a dc link voltage of ~300 V, and operating temperatures of 25 °C and 125 °C. The device could withstand subsequent short circuit successfully without any failure at both 25 °C and 125 °C. The short circuit current showed consistent dependency on the applied gate voltage, when it was varied from 0 V to 15 V.

Lateral source field-plated β-Ga2O3 MOSFET with recorded breakdown voltage of 2360 V and low specific on-resistance of 560 mΩ cm2

In this letter, lateral β-Ga2O3 MOSFETs with source field plate are fabricated on Si-doped homoepitaxial film on (010) Fe-doped semi-insulating β-Ga2O3 substrate. The drain extension in the source field plate effectively suppresses the peak electric field in the Ga2O3 channel, and improves the breakdown voltage greatly. Moreover, fluorinert FC-770 is used to reduce air breakdown potential during the breakdown testing. The breakdown voltage of the device with Lsd of 28 μm is measured as high as 2360 V, which is the highest value in reported lateral Ga2O3 MOSFET. Besides, Si-ion implantation is adopted to reduce the ohmic contact resistance (Rc). The value of specific on-resistance (Ron,sp) is calculated to be 560 mΩ cm2, which is a recorded value under such high breakdown voltage, and also lower than the theoretical limit of Si-based power devices under the same breakdown voltage.

Advanced HEMT Characteristics of Epitaxial Quality-improved GaN by Using Patterned Sapphire Substract

INTRODUCTIONAccomplishing with the booming market of personal communication services and the fifth generation (5G) mobile systems, the demands for high frequency and high power devices, such as radio frequency (RF) and microwave power amplifiers, becomes the most priority topic required to be dealt with. Considering the intrinsic electric properties, gallium nitride (GaN) is a suitable and important material for high-power device applications. However, there are many inevitable defects formed during epitaxial growth process due to the difference of the thermal expansion coefficient and the lattice constant mismatch between two materials. The reduction of the defect density is known to be the most fundamental way to fabricate high-power, high-efficient GaN electronic devices. In this paper, we proposed a critical technique to adjust the defects density of GaN, which was then introduced to fabricate HEMTs and yielded a well performed device.DEVICE FABRICATIONThe sapphire substrate used in this study was c-plane (0001), and was patterned with specific periodic structure with electron beam lithography in the first. The following wet-etching by using a mixture solution of sulfuric acid (H2SO4) and phosphoric acid (H3PO4) was processed to form the designed structure on the top of sapphire substrate as figure 1(a) and (b) shown. The substrate was then transferred to the epitaxial growth of GaN. The growth began with 3μm-thick insulating GaN as a device buffer layer, and then 30 nm unintentionally doped AlGaN layer doped 18% Aluminum. The as-prepared epi-wafer then processed with sequential procedures including, and the finial structure of HEMT were the same with the illustration of figure 1(c). MATERIAL QUALITY ANALYSIS In order to check the quality of epi-wafer, both Raman spectrum and EPD method were utilized here. We have compared two different regions of the sample, the PSS region and the planar region (without any surface structure). The shift of Raman peak and relative full width at half maximum (FWHM) were recorded and shown in the figure 2. From the figure 2(a), the peak-shift value from the PSS region is lower than planar region, and close to a free standing GaN (568.73 cm-1), which means less stress accumulated within the PSS region. Figure 2(b) shows that the FWHM in PSS region is 2.28, lower than 2.36 in planar region. Both the trends of Raman shift and FWHM are the same, which indicated a solid evidence of good crystal quality within PSS region.The result of EPD method has been observed by SEM, which is shown in figure 3. The dislocation density within the planar region is about 1.06 x 107 cm-2, which is higher than the PSS region (~2.54 x 106 cm-2). This result proves the better crystal quality of PSS region as well as the former two measurements. INFLUENCE OF SURFACE DEFECT DENSITY ON DIRECT CURRENT MEASUREMENT A further HEMT application of the quality-improved sample had been executed. Figure 4 shows the electronic properties of the sample with and without PSS. When the device’s gate is biased from -4V to 1V, the device with PSS exhibits higher drain than the planar one. In figure 4(a), when the gate voltage equal to 1V, the saturation current of the planar sample is 272.2 mA/mm, while the PSS sample is 323.4 mA/mm, about 18.8% increasing. As to the on-resistance (Ron) value, it reduces to 7.7 Ω-mm under very small drain voltage, which is a 65.9% decreasing comparing to the planar sample. The transduction value, which represents the gain of the gate voltage to the current, increases from 78.3 (planar) to 90.5 (PSS) mS/mm, about 15.6% increases. CONCLUSION We demonstrated a method to acquire a better crystal quality of GaN with PSS. The sample has been verified by Raman analysis and the EPD observation, both shown obvious improvement of crystal quality with PSS. The edge defect density has dropped about 1 order. The advance of crystal quality improved the electrical performance of HEMT. We believe that the method will be an effective and efficient technique that is capable to be applied to more semiconductor materials. Acknowledgments This study was supported financially by the Ministry of Science and Technology (MOST), Taiwan, under contract no. MOST 105-2221-E-002-185-MY3. References J.L. Hudgins, G.S. Simin, E. Santi,and M.A. Khan, “An Assessment of Wide Bandgap Semiconductors for Power Devices,” IEEE T POWER ELECTR, vol.18, pp.907-914 (2003).Yuen-Yee Wong ,et al.“The Roles of Threading Dislocations on Electrical Properties of AlGaN/GaN Heterostructure Grown by MBE” J ELECTROCERAM, 157 (7) H746-H749 (2010).Fabio Alessio Marino , et al. ‘’ Effects of Threading Dislocations on AlGaN/GaN High-Electron Mobility Transistors’’ IEEE T POWER ELECTR, VOL. 57, NO. 1, JANUARY (2010). Figure 1

(Invited) Gallium Oxide Power Devices Fabricated By Novel Processes

Innovative electric devices have been derived from new alloy systems for example AlAs-GaAs-InAs, AlP-GaP-AlAs-GaAs and AlN-GaN-InN. These alloy systems are consisted of binary compounds of same crystal structure and small lattice mismatches among them. However, it was hard work for oxides to construct an alloy of same crystals with small lattice mismatches because an oxide often takes various crystal polymorph including meta-stable phases. On the other hand, it may lead not only to a gold mine which contains novel functional crystals but also to a trigger to realize new functional devices. We found a new alloy concept of corundum-structured oxide crystals in 2013 toward successful synthesis of meta-stable phased α-Ga2O3, α-In2O3 thin films on sapphire substrates1)-3). A series of corundum-structured α-M2O3 (M= Al, Ga, In, Fe, Cr, V, Ti, Rh, Ir) is an attractive alloy system because they have unique physical properties including novel p-type semiconductor of α-Ir2O3 4). An α-Ga2O3 is one of the “ultra wide band-gap” semiconductor with a band gap of 5.3 eV3). Furthermore, it is advantageous for devices operating at high voltage with low on-resistance. Attempts were made to fabricate Schottky barrier diodes (SBDs). Since an α-Ga2O3 layer can be lifted off from a sapphire substrate, it is possible to fabricate vertical-structured SBDs with low series resistance. The on-resistance and breakdown voltage were 0.1 mW×cm2 and 531 V (SBD sample1) or 0.4 mW×cm2 and 855 V (SBD sample2), respectively5). The on-resistance value is seventh part of a commercially available SBD fabricated by SiC (0.7 mW×cm2). Moreover, aiming at showing potential as device materials, efforts have been given to fabricate MOSFETs with α-In2O3. These were fabricated using amorphous Al2O3 as a gate insulating layer and Au as gate and source electrodes. The device showed saturated drain current characteristics and clear pinch-off with subthreshold swing of 1.83 V/dec, field-effect mobility of 187 cm2/Vs, and effective mobility of 240 cm2/Vs. The relatively high mobility values are attractive for future evolution. Meanwhile, one of the most difficult attempts on exploring oxides is a discovery of new p-type semiconductors. Corundum-structured α-Rh2O3 and α-Ir2O3 were reported showing p-type conductivity only by Seebeck effect measurements because of their very small hall voltages6)-8). It is expected to be derived from larger energy level of Fermi-level than a bottom of conduction band at E-k dispersion in α-Rh2O3. An alloy of α-Rh2O3 and α-Ga2O3 were fabricated on α-Al2O3 substrates aiming to tune the Fermi-level of a α-Rh2O3. An α-(Rh,Ga)2O3 thin film showed clear p-type conductivity by hall effect measurements with a hole mobility of 1.0 cm2/Vs and carrier concentration of 7.6×1017/cm3, respectively. On the other hand, single-phased α-Ir2O3 thin films were fabricated for the first time. These also showed p-type conductivity by hall effect measurements. The detail of crystal-structure and electrical properties will present on the day. Part of this work was supported by “Strategic Innovation Program for Energy Conservation Technologies” of the New Energy and Industrial Technology Development Organization (NEDO).

Post-annealing processes to improve inhomogeneity of Schottky barrier height in Ti/Al 4H-SiC Schottky barrier diode

To improve the high resistance and low breakdown voltage (BV) of a 4H-SiC Schottky barrier diode (SBD), the metal annealing process is conventionally used; this process stabilizes the Schottky barrier height (SBH). In this paper, we apply a post-metal annealing process to 4H-SiC Ti-SBD chips and verify the effect of the changes on electrical characteristics based on the post-annealing process. The results of experiments show that the condition of 873K/30min annealing created a stable SBH and a low value of on-resistance (Ron), which improved inhomogeneity. Based on the results of EDX and TEM analysis, the cause of improved SBH at the condition of 30min was attributed to the generation of TiSix (which has a higher SBH than Ti). On the other hand, the improved value of Ron at the condition of 30min was attributed to the change to γ-phase Ti3Al (which has a low resistance because diffused Al is present) caused by proper annealing. However, when more heat is applied in the cases of 773K/60min and 873K/60min, Ron increased and the SBH decreased. The results of EDX and TEM analysis showed that the low SBH was caused by Al spiking, which created an Al Schottky junction with a lower SBH than that of the Ti Schottky junction. Higher Ron resulted from the change to α-TiAl phase at the Al–Ti interface layer because of excessive diffusion of Ti and Al, which is due to the overly applied heat.From the results produced by this work, we can enhance the Al–Ti 4H-SiC SBD electrical characteristics by applying a suitable post-annealing process.

Power-switching applications beyond silicon: Status and future prospects of SiC and GaN devices

Abstract

A low on-resistance silicon on insulator lateral double diffused metal oxide semiconductor device with a vertical drain field plate

To reduce the on-resistance and enhance the breakdown voltage of silicon on insulator (SOI) lateral double diffused metal oxide semiconductor (LDMOS) device at the same time, a low on-resistance SOI-LDMOS device with a vertical drain field plate and trench gate and trench drain (VFP-TGTD-SOI-LDMOS) is proposed. The device has the features as follows: first, a trench gate and a trench drain are adopted, which can widen the vertical current conduction area, shorten the lateral current conduction path, and lower the on-resistance. Secondly, a vertical field plate is used, which modulates the electric field around it, reduces the high electric field at the end of the drain electrode, and increases the breakdown voltage. The VFP-TGTD-SOI device is compared with a conventional SOI device, a trench gate SOI device, a trench gate and trench drain SOI device with the same dimensional device parameters using the two-dimensional semiconductor simulator MEDICI. The results show that under the condition of their own highest figure of merit (FOM), the specific on-resistance value of the VFP-TGTD-SOI device is reduced by 53%, 23%, and increased by 87%, respectively and the breakdown voltage is increased by 4% and reduced by 9% and increased by 45%, respectively. By comparing the FOMs of the four structures, it can be seen that the VFP-TGTD-SOI device has the highest FOM, which indicates that among the four structures, it maintains the lower on-resistance and holds the higher breakdown voltage at the same time.

Use N+ Buried Layer to Design a Low On-Resistance VDMOS

A novel structure of a VDMOS in reducing on-resistance is proposed and experimentally demonstrated with a 200V N-channel VDMOS. With this structure, the on-resistance value of the VDMOS is reduced by 19.6% than that of a traditional VDMOS structure as the breakdown voltage almost maintained the same value, and there is only one additional mask in processing this new structure VDMOS, which is easily fabricated. By TCAD tool, the specific on-resistance value will reduce by 23%, and the value by 33% will be realized when the device is fabricated in three epitaxies and four buried layers. The novel structure can be widely used in high-voltage VDMOS and BCD areas.

Investigation of Gate Degradation Characteristics of AlGaN/GaN HEMTs under PWM Stress

An investigation of gate degradation characteristics of AlGaN/GaN HEMTs under PWM stress is proposed in this paper. The device under testing features double source-connected field plates to reshape the surface electric field. A PWM signal with the operation frequency varied from 10 kHz to 1 MHz was applied to the gate electrode while the source was shorted to ground. HP 4155B was used to measure the gate characteristic of the device by every 30 minutes. The value of on-resistance shows an increase of 12.9 % after the device has been under stress for 30 minutes with the switching frequency of 10 kHz and the degradation is improved with higher switching frequency, while the threshold voltage and gate leakage current do not change significantly during the test.

Design and Architectural Assessment of 3-D Resistive Memory Technologies in FPGAs

Emerging nonvolatile memories (eNVMs) such as phase-change random access memories (PCRAMs) or oxide-based resistive random access memories (OxRRAMs) are promising candidates to replace Flash and Static Random Access Memories in many applications. This paper introduces a novel set of building blocks for field-programmable gate arrays (FPGAs) using eNVMs. We propose an eNVM-based configuration point, a look-up table structure with reduced programming complexity and a high-performance switchbox arrangement. We show that these blocks yield an improvement in area and write time of up to 3× and 33×, respectively, versus a regular Flash implementation. By integrating the designed blocks in an FPGA, we demonstrate an area and delay reduction of up to 28% and 34%, respectively, on a set of benchmark circuits. These reductions are due to the eNVM 3-D integration and to their low on-resistance state value. Finally, we survey many flavors of the technologies and we show that the best results in terms of area and delay are obtained with Pt/TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Pt stack, while the lowest leakage power is achieved by InGeTe stack.

A novel structure for improving the SEGR of a VDMOS

The mechanism of single-event gate-rupture in an N-channel VDMOS in a space radiation environment was analyzed. Based on the mechanism, a novel structure of VDMOS for improving single-event gate-rupture is proposed, and the structure is simulated and it is demonstrated that it can improve a VDMOS SEGR threshold voltage by 120%. With this structure, the specific on-resistance value of a VDMOS is reduced by 15.5% as the breakdown voltage almost maintains the same value. As only one mask added, which is local oxidation of silicon instead of an active processing area, the new structure VDMOS it is easily fabricated. The novel structure can be widely used in high-voltage VDMOS in a space radiation environment.

Anti-Parallel Circuit of Resistive Cu/TaOx/Pt Switches

ABSTRACTResistive switches are being explored as a candidate for ultra-dense memory as well as logic circuits. The advantages of the resistive switches include high switching speed and excellent scaling potential. Here, we report for the first time the switching behavior of anti-parallel connected resistive switches (APS), which is a composite device exhibiting bi-directional switching properties. Under the opposite voltage biases, the two anti-parallel cells are alternatively set and reset, rendering the APS switched in both directions. For appropriate ON resistance values and set and reset voltages the two anti-parallel switches can be both set in conductive states. An APS device can be realized in a single switch by two coexisting Cu and oxygen vacancy nanofilaments which are formed and ruptured under opposite voltage polarities. The described APS behavior is of interest to logic applications and in neural networks.

A novel structure in reducing the on-resistance of a VDMOS

A novel structure of a VDMOS in reducing on-resistance is proposed. With this structure, the specific on-resistance value of the VDMOS is reduced by 22% of that of the traditional VDMOS structure as the breakdown voltage maintained the same value in theory, and there is only one additional mask in processing the new structure VDMOS, which is easily fabricated. With the TCAD tool, one 200 V N-channel VDMOS with the new structure is analyzed, and simulated results show that a specific on-resistance value will reduce by 23%, and the value by 33% will be realized when the device is fabricated in three epitaxies and four buried layers. The novel structure can be widely used in the strip-gate VDMOS area.