Novel Error-Tolerant Voltage-Divider-Based Through-Silicon-Via Test Architecture

Abstract

A voltage-divider-based through-silicon-via (TSV) test architecture tests the TSV by using the voltage value differently divided according to TSV defects. This architecture is widely used for TSV testing owing to its small hardware overhead and high test speed. However, the existing voltage-divider-based TSV test architectures are vulnerable to process–voltage–temperature (PVT) variations and noise. In addition, they cannot effectively detect pinhole defects. This study proposes a novel error-tolerant voltage-divider-based TSV test architecture to address these problems. The proposed architecture reduces the test errors by appropriately adjusting the on-resistance value of each MOSFET and adding a compensator circuit. In addition, it effectively detects the pinhole defects by modifying the voltage divider structure and changing the MOSFET control method. Experimental results reveal that the proposed architecture promptly tests various TSV defects and significantly reduces the test errors.