On-resistance Value Research Articles

Comments on "1.88-$\hbox{m}\Omega \cdot \hbox{cm}^{2}$ 1650-V Normally on 4H-SiC TI-VJFET

The discussion section of paper “1.88-mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> 1650-V Normally on 4H-SiC TI-VJFET” which appeared in IEEE Transactions on Electron Devices, vol. 55, no. 8, August 2008, offers a comparative analysis between TI-VJFETs fabricated at USCI/Rutgers and VJFETs (SITs) fabricated at Northrop Grumman Electronic Systems (NGES) for power switching applications. I have a number of issues with this analysis which I wish to highlight. In addition, this paper claims VJFET performance records, which are dubious as they are based on on-resistance values obtained under bipolar operation and on blocking-voltages quoted at unspecified drain-current densities.

On the assessment of few design proposals for 4H-SiC BJTs

A theoretical design analysis using two-dimensional numerical computer aided design tool (TCAD) is presented for 4H-SiC BJTs. Compared to conventional design, a high p-doped thin layer between the base–emitter region is effective to suppress the surface recombination between the base–emitter region. Using a surface recombination layer (SR layer of 60nm thickness and acceptor doping of 1.0×1019cm−3) between base–emitter region, a peak gain of 410 was obtained at 100A/cm2. While a second epitaxy growth run is needed to utilize the advantage of this design, an alternate design with thin high doped (i.e., delta layer design) layer at the base–emitter junction is also interesting from the point of view of improving current gain with reduced on-resistance. A delta layer design thus produces a peak current gain of 300 at 100A/cm2 and on-resistance value of 4mΩ-cm2 at 300K. Compared to the experimental data of 4H-SiC BJTs, present simulated analysis provides superior performance in terms of current gain.

Electrical Characterization of Large Area 800 V Enhancement-Mode SiC VJFETs for High Temperature Applications

Prototype 800 V, 47 A enhancement-mode SiC VJFETs have been developed for high temperature operation (250 °C). With an active area of 23 mm2 and target threshold voltage of +1.25 V, these devices exhibited a 28 m room temperature on-resistance and excellent blocking characteristics at elevated temperature. With improved device packaging, on-resistance and saturation current values of 15 m and 100 A, respectively, are achievable.

High-Voltage 4H-SiC Bipolar Junction Transistors With Epitaxial Regrowth of the Base Contact

High-voltage (4-6 kV) 4H-SiC-based bipolar junction transistors were designed, fabricated, and characterized. Various design and process optimization techniques to improve the on state and the forward blocking performance of these devices were studied and incorporated. Using the conventional base contact implantation process, devices with blocking voltages up to 4 kV and specific on-resistance ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sp</sub> ) values higher than the unipolar limit (37 mOmegamiddotcm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ), with a current gain of ten in the active region, were experimentally demonstrated. A novel selective growth of p-contact-based process was developed and implemented. This, coupled with improvements in the termination design, resulted in enhancing the blocking voltage capability to 6 kV while simultaneously lowering the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sp</sub> to below the unipolar limit (28 mOmegamiddotcm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and current gain of four in the active region), for the same starting material. Evidence for the presence of conductivity modulation (for the first time) in high-voltage SiC BJTs was also shown experimentally.

Enhancement of breakdown voltage by AlN buffer layer thickness in AlGaN∕GaN high-electron-mobility transistors on 4in. diameter silicon

Enhancement of breakdown voltage (BV) with the increase of AlN buffer layer thickness was observed in AlGaN∕GaN high-electron-mobility transistors (HEMTs) grown by metalorganic chemical vapor deposition on 4in. Si. The enhancement of device performance with AlN buffer thickness (200 and 300nm) is due to the reduction of electrically active defects from Si substrate. The reduction of defects from Si with the increase of AlN thickness was confirmed by x-ray rocking curve measurements. Not much change has been observed in ON-state BV (BV:ON) values except in devices with 500-nm-thick buffer layer. About 46% enhancement in OFF-state BV (BV:OFF) was observed on 200μm wide HEMTs with 300nm thick AlN buffer layer when compared to HEMTs with 8nm thick AlN buffer layer. The location of junction breakdown in the device was identified as GaN∕AlN∕Si interface. The measured specific on-resistance (Ron) values for 200 and 400μm wide HEMTs with 300nm thick buffer layers were 0.28 and 0.33mΩcm2, respectively. About an order of low Ron was observed when compared with the reported values. The AlGaN∕GaN HEMTs on 4in. Si with thicker AlN buffer layers are suitable for high-power applications.

電力用半導体素子の極低温特性と極低温動作電力変換器の構成

In large superconducting coil applied systems, such as Superconducting Magnetic Energy Storage (SMES), nuclear fusion system and so on, large current leads for charging and discharging coils are needed, so that conduction heat through the leads may cause large heat losses and reduce efficiency of the system. Operating of a power supply (power converter) for a superconducting coil in the same cryostat together with the coil and converting the low voltage and high current power into high voltage and low current power in the cryostat, it will become possible to reduce the size of current leads and power losses of a power supply. Among existing power semiconductor devices such as thyristors and power transistors, power MOSFETs showed lower losses in low temperature region; they showed the minimum on-resistance value at around 70K. Utilizing this characteristic, a power converter using power MOSFETs and diodes was made and operated in a cryostat together with a superconducting coil. As a result, it was confirmed that the stable operation of a power converter in a cryostat is possible and that the size of current leads into a cryostat and power losses of a converter can be reduced.

Numerical and experimental comparison of vertical DMOSFET and UMOSFET

A numerical analysis has been performed to evaluate the relative performance of DMOS and UMOS power FETs based on a two-dimensional analytical approach. Since termination technology can achieve a near-ideal breakdown voltage for a given substrate resistivity and thickness, the breakdown voltage is determined by the intrinsic geometry of the unit cell in the vertical power MOSFETs (DMOSFET and UMOSFET). The authors analyse the on-resistance value each structure can offer while satisfying a specific blocking voltage requirement is given.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High-power conductivity-modulated FET's (COMFET's) with a p-type channel

In previous work, a conductivity-modulated field-effect transistor (COMFET) having drastically reduced on-resistance was described; that device was based on n-channel MOS technology. In this letter, we report the development of a complementary device-the p-channel COMFET. These new p-channel COMFET's have demonstrated dc on-resistance values as low as 0.07 Ω at 20 A (for a 3 mm × 3 mm pellet), while providing forward blocking voltages of 200-400 V. To our knowledge, this on-resistance value (normalized to the same active area) is lower than that of any p-channel power MOSFET (even those with blocking voltages of only 100 V) and as much as 30 times less than that of a p-channel MOSFET with a comparable blocking-voltage capability. Using suitable minority-carrier-lifetime control techniques, drain-current-decay times have been reduced from ≈ 30 µs to below 1 µs.

The COMFET—A new high conductance MOS-gated device

A new MOS gate-controlled power switch with a very low on-resistance is described. The fabrication process is similar to that of an n-channel power MOSFET but employs an n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> -epitaxial layer grown on a p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> substrate. In operation, the epitaxial region is conductivity modulated (by excess holes and electrons) thereby eliminating a major component of the on-resistance. For example, on-resistance values have been reduced by a factor of about 10 compared with those of conventional n-channel power MOSFET's of comparable size and voltage capability.