On-off Current Ratio Research Articles

Role of Seed Layer Crystalline Quality in Photoresponse Performance of Hydrothermally Grown ZnO Nanorods.

We investigated the effects of the crystalline state for seed layers (SLs) on the growth morphology and material characteristics for hydrothermally grown ZnO nanorods (NRs). For this, preheating (PH) at different temperatures (100–300 °C) and O2 plasma treatment (PT) for 9 min were performed during the growth of SLs on p-Si by the aqueous solution-based method to provide the characteristic change on the NR growth platform. An improvement in material properties was achieved from the ZnO NRs grown on the SL crystals of enhanced crystalline quality in terms of the increased preferred orientation (002), the higher UV emission with suppressed deep-level emissions, the recovery of O/Zn stoichiometry, and the reduction of various intrinsic defects. Ultraviolet photodiodes of a p-Si/n-ZnO-NR structure fabricated under the SL conditions of O2 PT and PH at 100 °C showed a significantly enhanced on-off current ratio of ~90 at +5 V and faster photoresponse characteristics presenting a reduction in the fall time from 16 to 9 s.

A new pocket-doped NCFET for low power applications: Impact of ferroelectric and oxide thickness on its performance

Negative capacitance field-effect transistor (NCFET) is a potential device that has exhibited an immense prospective to outplace conventional FETs because of their steep switching characteristics driven by ferroelectric gate stack. The negative capacitance in ferroelectrics yields a voltage step-up action that curtails the sub-threshold swing (SS) below 60 mV/decade. In this work, a device based on single gate NCFET (SG-NCFET) and a highly doped double pocket double gate (HDDP-DG-NCFET) with n++ pocket at the edge of source and drain channel junction are proposed to investigate the impact of the morphological modification on electrical parameters of NCFET. In addition, the effect of incorporating pocket in HfO2 based single gate and double gate NCFET is investigated that delivers steep SS and enhances the switching ratio. The device architecture is designed systematically to boost ION/IOFF ratio by optimizing the pocket thickness and ferroelectric parameters. Various scaling parameters are optimized to achieve an OFF current of 1.9 × 10−11 A/μm, 2.65 × 10−13 A/μm, ON-OFF current ratio of 108, 1010 and SS of 36.2 mV/decade, 25.5 mV/decade for SG-NCFET and HDDP-DG-NCFET, respectively. Finally, the proposed NCFET characteristics are compared to those of prevailing NCFET designs and the HDDP-DG-NCFET design emerges out to be a better solution for low-power applications.

Analysis of performance for novel pocket-doped NCFET under the influence of interface trap charges and temperature variation

This paper explores the DC characteristics and trap analysis of single gate NCFET (SG-NCFET) and highly doped double pocket double gate NCFET (HDDP-DG-NCFET) with spacer at different temperatures. The effect of temperature and the trap charges (Uniform and Gaussian) on various electrical parameters is investigated to determine the device's reliability. In addition, this work investigates the effect of interface (Si–SiO2) traps on the operation of NCFET, a potential developing technology that intends to achieve a steep sub-threshold slope. The presence of traps at interface degrades threshold voltage and sub-threshold swing. Hence, the work investigates the effect of various concentrations of trap at the oxide-semiconductor boundary on the sub-threshold swing, ON current, threshold voltage, OFF current, and current switching ratio of both the devices (SG-NCFET and HDDP-DG-NCFET). In this analysis, it has been observed that, sub-threshold slope (SS) increases with the temperature more rapidly than kT/q, representing the paraelectric effect, and surpasses kT/q after 450 K and 500 K for SG-NCFET and HDDP-DG-NCFET, respectively. Furthermore, it has been observed that the impact of temperature variation is greater on the switching ratio of the device in the presence of trap charges, while the opposite is valid for the OFF current. Finally, it is found that the Gaussian distribution of traps worsen the SS characteristics and ON-OFF current ratio of the device severely as compared to the uniform distribution of traps.

A novel normally-off GaN vertical Schottky source tunnel-junction field-effect transistor

In this work, a novel normally-off GaN vertical tunnel-junction field-effect transistor (VTJFET) was proposed and investigated by the Silvaco ATLAS simulator. The topology structure and operation mechanism of the VTJFET are completely different from those of previous GaN vertical power devices. The VTJFET exhibited normally-off operation with a threshold voltage VTH of +2.5 V. The specific on-resistance Ron,sp and the breakdown voltage BV were 1.78 mΩ cm2 and 2940 V, respectively. A high on-off current ratio of 1011 and high power figure of merit (FOM) of 4.9 GW/cm2 were achieved. The Ron,sp and BV of the VTJFET are affected by the doping concentration Ndrift and thickness Tdrift of the drift layer, and a record high optimized FOM of 7.4 GW/cm2 was obtained by varying Ndrift and Tdrift. The VTJFET is intrinsically normally-off and exhibited excellent performance, providing a new direction for the development of GaN vertical devices.

Colloidal MoS2 quantum dots for high-performance low power resistive memory devices with excellent temperature stability

Conventional memory technologies are facing enormous problems with downscaling, and are hence unable to fulfill the requirement of big data storage generated by a huge explosion of digital information. A resistive random access memory device (RRAM) is one of the most emerging technologies for next-generation computing data storage owing to its high-density stacking, ultrafast switching speed, high non-volatility, multilevel data storage, low power consumption, and simple device structure. In this work, colloidal MoS2 quantum dots (QDs) embedded in an insulating matrix of poly-(4vinylpyridine) (PVP) were used as an active layer to fabricate a RRAM device. The MoS2 QDs-PVP based RRAM device reveals an excellent nonvolatile resistive switching (RS) behavior with a maximum current on-off ratio (ION/IOFF) of 105. High endurance, long retention time, and successive “write-read-erase-read” cycles indicate high-performance RRAM characteristics. The ultimate power consumption by this RRAM device is considerably low for energy saving. In addition, the MoS2 QDs-PVP based device shows RS behavior even at 130 °C. High ION/IOFF, low operating power, high endurance, long retention time, and excellent stability with temperatures reveal that the MoS2 QDs-PVP based device can be a promising candidate for high-performance low power RRAM devices that can be operated at relatively higher temperatures.

Performance Improvement for Ge FinFET CMOS Inverter With Supercritical Fluid Treatment

Performance improvement on Ge nFinFET, pFinFET and CMOS inverter can be achieved by using a novel low temperature damage-free supercritical phase fluid (SCF) treatment. Thanks to effective reduction of unstable oxidation states, oxygen vacancies and interface traps, higher on-off current ratios (8×105 for pFinFET and 3.3×105 for nFinFET), lower S.S. (72 mV/dec), higher on current (>45% improvement) and better reliability in Ge FinFETs are achieved with a SCF treatment as compared with a remote plasma post-oxidation (PPO) one. Besides, a higher voltage gain (88 V/V) of Ge FinFET CMOS inverter is obtained with a SCF treatment in comparison with a remote PPO one.

Strain-Free Layered Semiconductors for 2D Transistors with On-State Current Density Exceeding 1.3 mA μm-1.

High-mobility and air-stable two-dimensional (2D) Bi2O2Se semiconductor holds promise as an alternative fast channel material for next-generation transistors. However, one of the key challenges remaining in 2D Bi2O2Se is to prepare high-quality crystals to fabricate the high-performance transistors with a high on-state current density. Here, we present the free-standing growth of strain-free 2D Bi2O2Se crystals. An ultrahigh Hall mobility of 160 000 cm2 V-1 s-1 is measured in strain-free Bi2O2Se crystals at 2 K, which enables the observation of Shubnikov-de Haas quantum oscillations and shows substantially higher (>4 times) mobility over previous in-plane 2D crystals. The fabricated 2D transistors feature an on-off current ratio of ∼106 and a record-high on-state current density of ∼1.33 mA μm-1, which is comparable to that of commercial Si and Ge n-type field-effect transistors (FETs) for similar channel length. Strain-free 2D Bi2O2Se provides a promising material platform for studying novel quantum phenomena and exploration of high-performance low-power electronics.

Phase Change Nanoelectromechanical Relay for Nonvolatile Low Leakage Switching

AbstractThe design, modeling, and experimental validation of a highly scalable phase change electromechanical relay are present. The Phase Change NEMS Relay (PCNR) is a nonvolatile mechanical relay actuated by the volumetric expansion of phase change material. GeTe is used as the active phase change material, and nonvolatile relay states are changed by converting it between amorphous and crystalline phases, which differ in volume by 10%. Phase conversion is induced by Joule heating an adjacent metal layer. Finite element analysis (FEA) models are developed to predict actuator temperature distributions and quench times for varied actuation pulses. Additional models are developed to simulate actuator deflection including reflow of molten phase change material during an actuation pulse. The smallest fabricated device has a heater footprint of 3 µm × 1 µm, with a 20 nm air‐gap. The FEA model, which calculates the actuation voltage, energy, and ON–OFF current ratio for this device to be 1.1 V, 42 nJ, and 108, respectively, are experimentally verified. A PCNR scaled down to a 15 nm × 5 nm heater footprint with a 2 nm air‐gap is predicted to actuate at 400 mV and 1.7 pJ.

Negative capacitance based phase-transition FET for low power applications: Device-circuit co-design

In this article, we have performed a comprehensive study into the Phase Transition Material based FinFET(PT-FinFET) device’s capabilities for low-power, energy-efficient applications through device circuit co-design perspective. Addressing its drawback at device and circuit level a novel device design known as the Negative Capacitance Phase Transition FinFET(NC-PTFinFET) is proposed by incorporating a ferroelectric material layer into the gate stack of the PTFinFET. The proposed device outperforms PTFinFET and FinFET in terms of SS and ON–OFF current ratio at the device level, as well as power and speed at the circuit level, and provides device tunability. With three case studies of embedded inverter chain, RO, and 2-bit RCA it was observed that the proposed NC-PTFinFET shows performance benefits in speed by reducing delay in these circuits with increasing NC thickness in comparison with the PTFinFET and FinFET. In contrast, increasing NC thickness in the proposed device energy efficiency is improved as compared to PTFinFET and FinFET.

The effect of passivation-layer process to amorphous InGaZnO thin-film transistors using back-channel etch method

In this work, based on the channel damage caused by source/drain etching and passivation-layer deposition, the effects of the passivation-layer process on amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) devices were studied by combining experimental investigation with simulation verification. In terms of experimental exploration, it was found that the back-channel N2O plasma treatment had a significant impact on the performance of the device, which was difficult to control. Hence, to achieve a low cost, the entire back-channel process was directly carried out as two steps of SiO x passivation-layer deposition and final thermal annealing. In the aspect of simulation verification, the influence of the passivation-layer deposition radio-frequency (RF) power and the annealing effect on the internal mechanism of the device was studied based on a high-concentration doped defect density of states (DOS) model (doping level was N D = 1020 cm−3). The experimental results demonstrated that the high-performance of an a-IGZO TFT device can be achieved by adjusting the RF power of SiO x passivation-layer deposition. It was more important that annealing after passivation-layer deposition was a critical step in the manufacture of high-performance TFTs. The device exhibited the ideal performance after annealing under 1000 W RF power, with a threshold voltage of 5.65 V, a saturation mobility of 12.87 cm2 V−1s−1, a subthreshold swing of 0.88 V dec−1, and a current on-off ratio of 2.62 × 10°8. In addition, using the DOS model, it was found that the SiO x passivation-layer process had a significant impact on the DOS distribution and the carrier distribution in the channel, which in turn caused the threshold voltage to drift. At last, the high uniformity and stability of an a-IGZO TFTs array on glass were characterized.

High mobility silicon indium oxide thin-film transistor fabrication by sputtering process

Amorphous silicon indium oxide (a-ISO) thin-films were deposited by sputtering process at room temperature for thin-film transistor (TFT) active channel applications. The amorphous nature of the deposited ISO thin films was confirmed by structural analysis and the films had an average surface roughness of ∼0.11 nm. The oxygen partial pressure was varied from 0 to 20% to deposit ISO active channel layers which showed a transition from conducting to semiconducting behaviour. The a-ISO TFT deposited with 5% oxygen partial pressure and post annealed at 100 °C exhibits a saturation mobility of 31.7 cm2/V.s, on-off current ratio of 2.3 × 1010, turn-on voltage of −5 V and sub-threshold swing of 0.25 V/dec. Bias stress analysis further confirms the stable operation of the ISO TFT devices. Silicon dopant acts as a strong carrier suppressor and enhances performance of a-ISO TFT devices.

Source pocket-engineered hetero-gate dielectric SOI Tunnel FET with improved performance

In this paper, we have studied and proposed a planar Tunnel FET device with source side SiGe pocket and hetero-gate dielectric structure that works by utilizing quantum mechanical Band-to-Band tunnelling (BTBT) mechanism. Simulation results obtained using a calibrated SILVACO TCAD device simulator show that the device exhibits good ambipolar performance because of the hetero-gate dielectric and the use of source pocket leads to steep point subthreshold swing of 4.90 mV/dec., an average subthreshold swing of 25.31 mV/dec. and a threshold voltage of 0.23 V. For including the hetero-gate dielectric, the variation in drain current values with high-κ dielectric length is analysed. The change in transfer characteristics with pocket parameters including pocket length and pocket doping is also reported. A 4 nm Si0.7Ge0.3 n+ pocket with doping concentration of 5 × 1019 cm−3 is found to show the maximum ON-OFF current ratio of 5.23 × 1011. This paper also performs a comparative study between different TFET structures and the analysis clearly highlights the potential of proposed Source Pocket-Engineered Hetero Gate Dielectric (SPE-HGD) TFET device for low-power and energy-efficient applications.

O2 and H2O Barrier-Based High Reliability and Stability Using Polytetrafluoroethylene Passivation Layer for Solution Processed Indium Oxide Thin Film Transistors

The excellent chemical stability and hydrophobicity of Polytetrafluoroethylene (PTFE) polymer lead to its applicability in high-performance flexible electronic appliances. Though the detailed investigation for PTFE passivated metal oxide thin-film transistors (TFTs) is still lacking. Here, we report the highly stable oxygen barrier based on the PTFE passivation layer (PVL) spin-coated upon the lowtemperature solution-processed indium oxide (In₂O₃) TFTs. Particularly, by using the solution-process method, fabrication cost and multiple time-consuming steps are eliminated in the counterpart of the radio frequency magnetron sputtering. The PTFE PVL can significantly suppress the adsorption of surrounding moisture and oxygen from environments owing to its most chemically robust carbon-fluorine bond. In addition, the comprehensive electrical performance in terms of the saturation mobility, on-off current ratio, threshold voltage, subthreshold swing, and interface trap density of the In₂O₃ TFTs passivated with different weight ratios of PTFE are compared. The results show that 1 wt.% PTFE passivated In2O3 TFT demonstrates a drastically reduced threshold voltage and highest stability under constant bias. Consequently, oxygen barrier-based PTFE is a promising PVL material for various emerging electronic devices.

Trends in performance characteristics and modelling of oxide based TFT

This paper reviews Thin Film Transistors (TFTs) and its performance characteristics. Specific focus has been given on the performance characteristics of oxide based TFT because of the wide range of applications of such TFT’s. The oxide TFT devices are having excellent potential in the near future as active matrix displays. Due to fast expansion of electronics industry, modelling of TFT’s and ability to simulate the circuit behavior prior to production is important. The parameters such as grain boundary defect, mobility, on-off current ratio, thermal stability etc. are important factors need to consider and capture while modeling. This paper also finally discusses the importance of programming voltage, process temperature charge leakage and storage capacity of memory devices.

Hybrid La2O3-cPVP Dielectric for Organic Thin Film Transistor Applications

In this work, we have studied the electrical performance of cross-linked polyvinyl phenol (cPVP) modified lanthanum oxide (La2O3) bilayer dielectric film in pentacene thin film transistors (TFT). A simple spin-coating and room temperature operated cross-linking reaction of the hydroxyl moieties of PVP and the nitrogen groups of PMF were carried out to form the cross-linked PVP. The deposition of a thin 30 nm cPVP layer over the La2O3 layer provided a low leakage current (<10−7 A cm−2), causing a reduction in the interface trap density. Besides, the modified surface properties of the La2O3 layer were favorable for the growth of pentacene organic semiconductors. As a result, the current on-off ratio and the sub-threshold slope was improved from 104 and 1.0 V/decade to 105 and 0.67 V/decade. The La2O3∕cPVP pentacene TFT operated at −10 V also exhibited improvement in the field-effect mobility to 0.71 cm2 Vs−1 from 0.48 cm2 Vs−1 for the single-layer La2O3 (130 nm) device. Thus, our work demonstrates that the rare earth oxide La2O3 with cPVP is an excellent dielectric system in the context of emerging transistors with hybrid polymer gate dielectrics.

Narrow Sub-Fin Technique for Suppressing Parasitic-Channel Effect in Stacked Nanosheet Transistors

A new approach of narrowing sub-fin with little extra process cost for suppressing parasitic-channel-effect (PCE) on vertically-stacked horizontal gate-all-around (GAA) Si nanosheet field-effect-transistors (NS-FETs) is proposed. The proposed sub-fin design demonstrates systematical technical advantages by calibrated 3D TCAD simulation, including 70% reduction in sub-channel gate-induced drain leakage (GIDL) current, over 20% promotion for on-off current ratio ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{\mathrm{ on}}/\text{I}_{\mathrm{ off}}$ </tex-math></inline-formula> ) as well as improvement in sub-threshold slope (SS). The revealed narrow sub-fin offers nearly 10% on-state current promotion and gate controllability improvement for the NS-FETs with relatively lower ground-plane-concentration. The narrow sub-fin technique provides a new approach for suppressing PCE in the NS-FETs and indicates a promising supplementary technology adopted for the optimization of NS-FET fabrication process in sub-3nm technology node.

Silicon doping and N2 annealing effects on Zn3N2 thin film transistors

Zn3N2 has high mobility >100 cm2V−1s−1, but its intrinsic carrier concentration (1018-1020 cm−3) has limited its application as thin-film transistor active material. In this work, Si-doped Zn3N2 (ZSN) thin-film transistors (TFTs) were fabricated by magnetron sputtering and annealed in N2 ambient. The influences of Si doping content, annealing temperature and active layer thickness on ZSN TFTs were investigated. It was found that annealing temperature up to 250 °C improved the performances of ZSN TFTs. The threshold voltage (Vth) positively shifts along with improving subthreshold swing (SS) as Si doping content increases. Moreover, further SS improvement was observed by reducing active layer thickness. The ZSN TFT with overall optimal performances exhibited typical Vth of 1.4 V, on-off current ratio of 2.9 × 106, subthreshold swing of 0.86 V·dec−1 and field-effect mobility of 0.69 cm2V−1s−1. Finally, the bias stress stability and the influence of oxide passivation on ZSN TFTs were investigated.

Performance analysis of different material based dual electrode doping-less TFET

In this work, the charge plasma based dual electrode doping-less tunnel FETs (DEDLTFET) is simulated with the use of different materials such as silicon (Si-DEDLTFET), Silicon-germanium (SiGe-DEDLTFET) and SiGe at Source (SiGe Source DEDLTFET). The charge plasma technique is used to create source and drain region on an intrinsic body by selecting appropriate work function of metal electrode. The paper provides the comparison among devices on the basis of RF parameters. The on-state current (ION) for SiGe source DEDLTFET, SiGe-DEDLTFET and DEDLTFET are 1.84x10-4, 8.75x10-5 and 8.11x10-6 A/µm respectively for similar off-state current (IOFF). This result show that SiGe source DEDLTFET device provides better drive current along with improved ON-OFF current ratio (ION/IOFF) and subthreshold slope (SS). Improved transconductance (gm) and cut-off frequency (fT) show that the hetero-material device has better RF performance while comparing with the other two devices. Copyright © 2017 VBRI Press.

Novel Metal Chalcogenide–Conducting Polymer Hybrid Material for Electronic Memory Devices

New hybrid (organic–inorganic) material based on nanocrystalline CdSe capped with EDTA and poly(O-toluidine) doped with camphor sulfonic acid (POT-CSA) is processed from solution and characterized in order to relate the device function (optical absorption, charge separation and transport properties) to active-layer properties and device parameters. POT/CdSe hybrid material has been synthesized using physical mixing method. X-ray diffraction (XRD) and scanning electron microscopy (SEM) are used to investigate the structural and morphological properties. The organic–inorganic composite system was applied as an active device component to demonstrate the electrical memory effects. The device exhibited a nonvolatile, resistive switching performance with a constant ON–OFF current ratio. The nonvolatile behavior was confirmed by applying a 2.5-V read pulse.

Complementary Two-Dimensional (2-D) FET Technology With MoS2/hBN/Graphene Stack

This paper demonstrates a complementary 2-D field-effect transistor (FET) technology with molybdenum disulfide (MoS2) as the active film, hexagonal boron nitride (hBN) as the gate dielectric, and graphene as the gate electrode. The active region of the n-channel (n-FET) and p-channel (p-FET) devices are formed by undoped and Nb-doped MoS2, respectively. The complementary FETs have the desirable threshold voltage polarity, similar current drive, and high on-off current ratios of more than 106. A complementary metal-oxidesemiconductor (CMOS) inverter has been fabricated and the measured gain is about 14 with 90% noise margin at a 2 V power supply.