On-current Variations Research Articles

A comprehensive Pelgrom-based on-current variability model for FinFET, NWFET and NSFET

We present a novel Pelgrom-based predictive (PBP) model to estimate the impact of variability on the on-current of different state-of-the-art semiconductor devices. In this work, we focus on two of the most problematic sources of variability, the metal grain granularity (MGG) and the line edge roughness (LER). This model allows us to make an accurate prediction of the on-current standard deviation σIon, being the relative error of the predicted data lower than 8% in 92% of the studied cases. The PBP model entails an immense reduction in the computational cost since once it is calibrated for an architecture, the prediction of the impact of a variability on devices with any given dimension can be made without any further simulations. This model could be useful for predicting the effect of variability on future technology nodes.

Cause analysis of width-dependence of on-current variability in thin gate-all-around silicon nanowire MOSFET

In this study, the width dependence of on-current variability in extremely narrow gate-all-around silicon nanowire MOSFET down to 2 nm width is analyzed by variability decomposition into components as well as analyzing the Pelgrom plot. It is found that the current variability rapidly increases below 4 nm mainly due to quantum-effect-induced threshold voltage variability and silicon-thickness-fluctuation-induced mobility fluctuation. The current variability becomes even worse in 2 nm, which is fundamentally caused by line width roughness.

Negative capacitance FETs for energy efficient and hardware secure logic designs

Negative capacitance field effect transistors (NCFETs) have attracted good attention for energy efficient circuit designs. However, there are no clear design insights with NCFET based circuit designs for energy efficient and hardware secure applications. However, the lack of clear design insights make energy efficient and hardware secure NCFET circuit design more challenging. This paper presents important design insights and scope of NCFETs for energy efficient and hardware secure logic design at scaled supply voltages. Initially, NCFET device characteristics have been analyzed by varying the ferroelectric layer thickness (tfe) to identify optimum device performance window. At 40 nm technology node, NCFET device demonstrates enhanced characteristics for logic design with tfe in the range of 3 nm–5 nm due to steep subthreshold swing characteristics. NCFET with tfe of 5 nm exhibits 1.22 × higher ON current, 66 × lower leakage current and a SS of 50mV/dec compared to baseline MOSFET (tfe = 0 nm). Further, NCFET based static complementary inverter design exhibits better performance and higher energy efficiency compared to baseline MOSFET. NCFET inverter with tfe of 3 nm achieves optimum performance in terms of voltage transfer characteristics, differential gain, and noise margins. In addition, NCFET with tfe of 3 nm shows minimum energy consumption with the different supply voltages in the range of 0.6–0.8 V. Moreover, NCFET based buffer, logic gates and half-adder designs with tfe of 3 nm achieve approximately 3 × lower energy consumption compared to baseline designs. Apart from this, the NCFET designs exhibit 2 × higher ON current variations, 12 × higher inverter delay variations, and 3.1 × higher ring oscillator frequency variations compared to baseline designs against 5% process parameter variations at a supply voltage of 0.5 V. With the higher variations resulted from ferroelectric layer, NCFET demonstrate the potential and suitability towards the design of hardware security primitives like physically unclonable function (PUF) and true random number generator (TRNG).

A Unified Model of Drain Current Local Variability due to Channel Length Fluctuation for an n-channel Eδ DC MOS Transistor

A drain current local variability compact model due to random fluctuation of channel length induced by line edge roughness/line width roughness (LER/LWR) is derived here. The random fluctuation of channel length leads to correlated fluctuations of threshold voltage and effective mobility of the current carriers. Therefore, an unified compact model is required to combine all the causes. Our model is based on the principle of propagation of variance. For the model verification purpose, calibrated technology computer aided design (TCAD) simulation platform is extensively used for all possible bias regions and several LER profile parameters. Channel profile optimization is critically studied with respect to different LER parameters, aiming reduction of ID variability. The model is further extended for SOI (Silicon-on-insulator) transistor and validated with literature data of threshold voltage and on-current variability.

Improved statistical variability and delay performance with junctionless inserted oxide FinFET

Junctionless inserted oxide FinFET (JL-iFinFET) is presented, its performance metrics are quantified and compared with JL-FinFET and JL-Stacked-Nanowire-FET (JL-SNWFET) respectively for the same foot-print on the wafer. The Random-Dopant-Fluctuation (RDF) and Metal-Gate-Granularity (MGG) are major variability sources in nano-transistors. Impedance Field Method is used to analyze the statistical variability performance of all three structures caused by RDF and MGG. The result shows JL-SNWFET provides superior DC figure-of-merits and 40% less statistical variability than JL-FinFET with a 10% increase in delay and considerable increase in fabrication complexity. The JL-iFinFET offers 30% lesser process-induced threshold voltage and on-current variations compare to JL-FinFET, without deteriorating delay and RF metrics due to its superior electrostatic control over the channel and multi-channel configuration. Fabrication of JL-iFinFET is also possible without adding much complexity in FinFET process it can be a major contender for continued scaling with JL-Transistors (JLTs).

Process Variation-Induced Contact Resistivity Variability in Nanoscale MS and MIS Contacts

This article presents contact resistivity variability (CRV) in metal-semiconductor (MS) and metal-interfacial layer (IL)-semiconductor (MIS) contacts on Ge and Si source/drain regions resulting from process-induced random dopant fluctuation (RDF) and IL thickness variation (ILTV). CRV is modeled by combining the effect of RDF and ILTV in statistical simulations incorporating Fermi-level pinning physics. CRV is also shown to have a direct and significant impact on 7-nm FinFET On-current variability. The choice of contact architecture depends strongly on the source/drain doping. RDF dominates at low doping and MIS contacts provide lower CRV as well as lower resistivity ( $\rho _{c}$ ) due to a lower contact barrier height. Impact of RDF decreases and that of ILTV increases with increasing doping resulting in lower CRV with comparable $\rho _{c}$ for MS contacts.

Drift-Diffusion Versus Monte Carlo Simulated ON-Current Variability in Nanowire FETs

Variability of semiconductor devices is seriously limiting their performance at nanoscale. The impact of variability can be accurately and effectively predicted by computer-aided simulations in order to aid future device designs. Quantum corrected (QC) drift-diffusion (DD) simulations are usually employed to estimate the variability of state-of-the-art non-planar devices but require meticulous calibration. More accurate simulation methods, such as QC Monte Carlo (MC), are considered time consuming and elaborate. Therefore, we predict TiN metal gate work-function granularity (MGG) and line edge roughness (LER) induced variability on a 10-nm gate length gate-all-around Si nanowire FET and perform a rigorous comparison of the QC DD and MC results. In case of the MGG, we have found that the QC DD predicted variability can have a difference of up to 20% in comparison with the QC MC predicted one. In case of the LER, we demonstrate that the QC DD can overestimate the QC MC simulation produced variability by a significant error of up to 56%. This error between the simulation methods will vary with the root mean square (RMS) height and maximum source/drain $n$ -type doping. Our results indicate that the aforementioned QC DD simulation technique yields inaccurate results for the ON-current variability.

Random Dopant-Induced Variability in Si-InAs Nanowire Tunnel FETs: A Quantum Transport Simulation Study

In this letter, we report a quantum transport simulation study of the impact of random discrete dopants (RDDs) on Si-InAs nanowire p-type Tunnel FETs. The band-to-band tunneling is simulated using the non-equilibrium Green’s function formalism in effective mass approximation, implementing a two-band model of the imaginary dispersion. We have found that RDDs induce strong variability not only in the OFF-state but also in the ON-state current of the TFETs. Contrary to the nearly normal distribution of the RDD-induced ON-current variations in conventional CMOS transistors, the TFET’s ON-currents variations are described by a logarithmic distribution. The distributions of other figures of merit (FoM) such as threshold voltage and subthreshold swing are also reported. The variability in the FoM is analyzed by studying the correlation between the number and the position of the dopants.

FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability

Performance, scalability, and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3-D simulation tools. Two experimentally based devices, a 25-nm gate length FinFET and a 22-nm GAA NW are modeled and then scaled down to 10.7- and 10-nm gate lengths, respectively. A TiN metal gate work-function granularity (MGG) and line edge roughness (LER) induced variability affecting OFF and ON characteristics are investigated and compared. In the OFF-region, the FinFETs have over an order of magnitude larger OFF-current that those of the equivalent GAA NWs. In the ON-region, the 25/10.7-nm gate length FinFETs deliver 20/58% larger ON-current than the 22/10-nm gate length GAA NWs. The FinFETs are more resilient to the MGG and LER variability in the subthreshold compared to the GAA NWs. However, the MGG ON-current variability is larger for the 10.7-nm FinFET than that for the 10-nm GAA NW. The LER ON-current variability depends largely on the RMS height; whereas a 0.6-nm RMS height yields a similar variability for both FinFETs and GAA NWs. Finally, the industry preferred 〈110〉 channel orientation is more resilient to the MGG and LER variability in both architectures.

Impact of Process Variations on Negative Capacitance FinFET Devices and Circuits

We report on the impact of process variations on short-channel negative capacitance (NC)-based FinFETs through statistical Monte Carlo simulations using a physics-based model of NC-FinFETs. We find that relative to regular FinFETs, the impact of geometrical variability can be lesser or higher in NC-FinFETs in different regimes of device operation and is strongly dependent on the nominal ferroelectric (FE) thickness ( ${t}_{\text{fe}}$ ). The contribution of the FE layer to the overall variability behaves non-monotonically with increase in the nominal ${t}_{\text {fe}}$ . While the OFF-current and threshold voltage variabilities scale down, the ON-current variability does not follow a monotonic trend with increase in the nominal ${t}_{\text{fe}}$ . We also show that although relative to the regular FinFET-based ring oscillator (RO) circuit, the NC-FinFET-based RO (NC-RO) circuit displays increased immunity to process variation induced delay variability, the trend is non-monotonic with regard to ${t}_{\text{fe}}$ scaling.

Metal Grain Granularity Study on a Gate-All-Around Nanowire FET

The impact of the metal grain granularity (MGG) variations on subthreshold and ON-current of a 22-nm gate length Si gate-all-around (GAA) nanowire (NW) field-effect transistor (FET) is analyzed by assessing five figures-of-merit: threshold voltage ( ${V}_{T}$ ), OFF-current ( ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ ), subthreshold slope (SS) and drain-induced-barrier-lowering at low ( ${V}_{D}={50}$ mV) and high ( ${V}_{D}={1.0}$ V) drain biases, and ON-current variability at the high drain bias. We assume a TiN metal gate with four grain sizes (GS): 10, 7, 5, and 3 nm. The simulations carried out employ: 1) a 3-D finite element (FE) drift-diffusion (DD) simulator with density-gradient (DG) quantum corrections (QC) in the subthreshold region and 2) a 3-D FE Monte Carlo (MC) simulation toolbox with Schrodinger equation QC for the ON-current. We have found that the ${\sigma }{V}_{T}$ due to the MGG variability is 10% higher in the GAA-NW FET (GS of 10 nm) than in a 20-nm gate FinFET. For a GS of 3 nm, the variability becomes comparable between the GAA-NW FET and the FinFET. Comparison against the line-edge-roughness (LER) variability shows that the MGG (GS of 10 nm) affects ${\sigma }{V}_{T}~92$ % more than the LER (root-mean-square height of 0.85nm and correlation length of 20 nm). Finally, the ON-current of the FinFET (GS of 10 nm, ${V}_{D}=\textsf {0.9}$ V) has a 43% higher ${\sigma }{I}_{ \mathrm{\scriptscriptstyle ON}}$ than that of the GAA-NW (GS of 10 nm, ${V}_{D}=\textsf {1.0}$ V) making the GAA-NW FETs a much better solution for sub-10-nm technology nodes.

Comparison of Fin-Edge Roughness and Metal Grain Work Function Variability in InGaAs and Si FinFETs

The fin-edge roughness (FER) and the TiN metal grain work function (MGW)-induced variability affecting OFF and ON device characteristics are studied and compared between a 10.4-nm gate length In0.53Ga0.47As FinFET and a 10.7-nm gate length Si FinFET. We have analyzed the impact of variability by assessing five figures of merit (threshold voltage, subthreshold slope, OFF-current, drain-induced-barrier-lowering, and ON-current) using the two state-of-the-art in-house-build 3-D simulation tools based on the finite-element method. Quantum-corrected 3-D drift-diffusion simulations are employed for variability studies in the subthreshold region while, in the ON-region, we use quantum-corrected 3-D ensemble Monte Carlo simulations. The In0.53Ga0.47As FinFET is more resilient to the FER and MGW variability in the subthreshold compared with the Si FinFET due to a stronger quantum carrier confinement present in the In0.53Ga0.47As channel. However, the ON-current variability is between 1.1 and 2.2 times larger for the In0.53Ga0.47As FinFET than for the Si counterpart, respectively.

Comprehensive study of the statistical variability in a 22 nm fully depleted ultra-thin-body SOI MOSFET

A comprehensive study of statistical variability (SV) in scaled, fully-depleted (FD) SOI n-channel MOSFET with a physical gate length of 22nm is reported. The impact of random discrete dopant (RDF), line edge roughness (LER) and metal gate granularity (MGG) on threshold voltage (VTH), drain-induced-barrier-lowering (DIBL) and on-current (Ion) are analyzed both individually and combined together. Results indicate that although MGG is the dominated variability source in the FD-SOI transistor, RDF has critical impact on the on-current variability. Moreover, the combination of RDF and LER can still dramatically modulate short channel effect behavior in the transistor.

(Invited) On-Current Variability Sources of FinFETs: Analysis and Perspective for 14nm-Lg Technology

On-current (Ion) variability in FinFETs is comprehensively investigated with regard to contributions of three independent sources, namely, threshold voltage (Vt), parasitic resistance (Rpara) and trans-conductance (Gm) variations. Origins of the Vt and Rpara variations are further analyzed. The Gm variation exhibits a linear relationship in Pelgrom plot as well as the Vt variation, and is not reduced with scaling the gate dielectric thickness unlike the Vt variation. Using the scalability data for the variation components, perspective of the Ion variability for 14-nm FinFETs reveals that the Gm variation will be the dominant Ion variation source. A solution to reduce the Gm variation for FinFETs is also proposed.

Investigation on Variability in Metal-Gate Si Nanowire MOSFETs: Analysis of Variation Sources and Experimental Characterization

The characteristic variability in gate-all-around (GAA) Si nanowire (NW) metal-oxide-semiconductor field-effect transistors (SNWTs) is analyzed and experimentally investigated in this paper. First, the main variation sources in SNWTs are overviewed, with the detailed discussion on the specific sources of NW cross-sectional shape variation, random dopant fluctuation in NW source/drain extension regions and NW line-edge roughness (LER). Then, following the measurement-modeling approach, via calibrated statistical simulation that is based on the modified analytical model for GAA SNWTs with corrections of quantum effects and quasi-ballistic transport, the variability sources in SNWTs are experimentally extracted from the measured devices with 10-nm-diameter NW channels and TiN metal gate. The results indicate that NW radius variation and metal-gate work function variation dominate both the threshold voltage and on-current variations due to the ultrascaled dimensions and strong quantum effects of GAA NW structure. The NW LER also contributes, but relatively less, to the threshold voltage variation.

Hierarchical Simulation of Statistical Variability: From 3-D MC With “ ab initio” Ionized Impurity Scattering to Statistical Compact Models

Quantum corrections based on density gradient formalism, recently introduced in the 3-D Monte Carlo (MC) module of the Glasgow “atomistic” simulator, are used to simultaneously capture quantum confinement effects as well as “ab initio” ionized impurity scattering. This has allowed us to consistently study the impact of transport variability due to scattering from random discrete dopants on the on-current variability in realistic nano-CMOS transistors. Such simulations result in an increased drain current variability when compared with the drift diffusion (DD) simulation. For the first time, a method that is used to accurately transfer the increased on-current variability obtained from the “ ab initio” MC simulations to the DD simulations is subsequently presented. The MC-corrected DD simulations are used to produce the target I-V characteristics from which the statistical compact models are extracted for use in preliminary design kits at the early stage of new technology development.

On the bandstructure velocity and ballistic current of ultra-narrow silicon nanowire transistors as a function of cross section size, orientation, and bias

A 20 band sp3d5s∗ spin-orbit-coupled, semiempirical, atomistic tight-binding model is used with a semiclassical, ballistic field-effect-transistor model, to theoretically examine the bandstructure carrier velocity and ballistic current in silicon nanowire (NW) transistors. Infinitely long, uniform, cylindrical, and rectangular NWs, of cross sectional diameters/sides ranging from 3–12 nm are considered. For a comprehensive analysis, n-type and p-type metal-oxide semiconductor (NMOS and PMOS) NWs in [100], [110], and [111] transport orientations are examined. In general, physical cross section reduction increases velocities, either by lifting the heavy mass valleys or significantly changing the curvature of the bands. The carrier velocities of PMOS [110] and [111] NWs are a strong function of diameter, with the narrower D=3 nm wires having twice the velocities of the D=12 nm NWs. The velocity in the rest of the NW categories shows only minor diameter dependence. This behavior is explained through features in the electronic structure of the silicon host material. The ballistic current, on the other hand, shows the least sensitivity with cross section in the cases where the velocity has large variations. Since the carrier velocity is a measure of the effective mass and reflects on the channel mobility, these results can provide insight into the design of NW devices with enhanced performance and performance tolerant to structure geometry variations. In the case of ballistic transport in high performance devices, the [110] NWs are the ones with both high NMOS and PMOS performance as well as low on-current variations with cross section geometry variations.

Design Space for Low Sensitivity to Size Variations in [110] PMOS Nanowire Devices: The Implications of Anisotropy in the Quantization Mass

A 20-band sp(3)d(5)s* spin-orbit-coupled, semiempirical, atomistic tight-binding model is used with a semiclassical, ballistic, field effect transistor (FET) model, to examine the ON-current variations to size variations of [110]-oriented PMOS nanowire devices. Infinitely long, uniform, rectangular nanowires of side dimensions from 3 to 12 nm are examined and significantly different behavior in width versus height variations are identified and explained. Design regions are identified, which show minor ON-current variations to significant width variations that might occur due to lack of line width control. Regions which show large ON-current variations to small height variations are also identified. The considerations of the full band model here show that ON-current doubling can be observed in the ON-state at the onset of volume inversion to surface inversion transport caused by structural side size variations. Strain engineering can smooth out or tune such sensitivities to size variations. The cause of variations described is the structural quantization behavior of the nanowires, which provide an additional variation mechanism to any other ON-current variations such as surface roughness, phonon scattering, etc.

The Impact of Random Dopant Aggregation in Source and Drain on the Performance of Ballistic DG Nano-MOSFETs: A NEGF Study

We have studied the effect of deviations from doping uniformity in source and drain on the performance of sub-20 nm silicon double-gate MOSFET devices. The study is motivated by recent direct observation of such inhomogeneities in small MOSFET devices. The model assumes a continuous charge distribution with randomly located regions of high doping. Individual dopants are not resolved. Impurity scattering in the source and drain regions is neglected. The current-voltage characteristics are computed for devices that differ only in the microscopic arrangement of the randomly distributed high doping regions. We have also studied devices that differ in the number of these clusters. An ensemble of devices with fluctuating numbers of clusters has been constructed based on a Gaussian distribution centered on the mean cluster number derived from the average doping concentration in the source/drain. The impact of high doping clusters, particularly on charge injection, has been studied in detail for the first time using full quantum simulation based on the 2D nonequilibrium Green function approach coupled self-consistently to Poisson's equation. We have assumed an average lateral symmetry for the double-gate MOSFET. Therefore, we only consider inhomogeneities in doping in the plane of the simulation. The devices studied have 12 nm channel lengths which allows the approximation of ballistic quantum transport through the self-consistent electrostatic potential landscape of the device. The computed current-voltage characteristics are monotonic and they are most strongly affected by the fluctuations in the total number of high doping regions. Fluctuations in the spatial configuration of clusters have a lesser effect. Threshold voltages shifts around 100 mV and on-current fluctuations around 50% are obtained from the simulations. However, the subthreshold slope remains almost independent of the microscopic cluster distribution. The on-current variations are considerably larger than those predicted from classical modeling.