On-chip Wiring Research Articles

Inductance formulas adapted for direct use in Spice simulators

Accurate analytical formulas for the self and mutual inductance of rectangular wires, that only require basic arithmetic expressions, are presented. The main objective of these formulas is their use as user defined parameterised expressions in Spice and similar applications, offering a convenient way to simulate and optimise the inductive behaviour of on-chip metal wires.

Effect of Additives on Shape Evolution during Electrodeposition: II. Parameter Estimation from Roughness Evolution Experiments

Numerical analysis procedures are used to identify the most sensitive parameters and estimate their values based on experimental measurements and a hypothesized mechanism for the effect of additives on copper electrodeposition. The electrolysis system consists of an acid copper sulfate bath containing accelerator, suppressor, and leveler additives in the range of concentrations typically used for deposition of on-chip wiring interconnections. Experimental measurements, obtained with an impinging jet apparatus, included surface roughness evolution and potential-time curves under constant current deposition in a set of 36 electrolyte compositions, selected by a D-optimal design procedure. The hypothesized additive mechanism consisted of a set of 15 surface reactions and 3 homogeneous chemical reactions. A mathematical model was composed that couples kinetic Monte Carlo simulation (for roughness evolution) with a finite volume method (for computing surface concentrations and potential). After identifying the most sensitive parameters and estimating their values, the surface concentrations of key species associated with the additive mechanism were simulated. The methods reported here are reusable and may be applied to other applications beyond the copper electrodeposition used here for its initial development.

A spatial path scheduling algorithm for EDGE architectures

Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE architectures are one example of communication-exposed microarchitectures in which the compiler forms dataflow graphs that specify how the microarchitecture maps instructions onto a distributed execution substrate. This paper describes a compiler scheduling algorithm called spatial path scheduling that factors in previously fixed locations - called anchor points - for each placement. This algorithm extends easily to different spatial topologies. We augment this basic algorithm with three heuristics: (1) local and global ALU and network link contention modeling, (2) global critical path estimates, and (3) dependence chain path reservation. We use simulated annealing to explore possible performance improvements and to motivate the augmented heuristics and their weighting functions. We show that the spatial path scheduling algorithm augmented with these three heuristics achieves a 21% average performance improvement over the best prior algorithm and comes within an average of 5% of the annealed performance for our benchmarks.

A spatial path scheduling algorithm for EDGE architectures

Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE architectures are one example of communication-exposed microarchitectures in which the compiler forms dataflow graphs that specify how the microarchitecture maps instructions onto a distributed execution substrate. This paper describes a compiler scheduling algorithm called spatial path scheduling that factors in previously fixed locations - called anchor points - for each placement. This algorithm extends easily to different spatial topologies. We augment this basic algorithm with three heuristics: (1) local and global ALU and network link contention modeling, (2) global critical path estimates, and (3) dependence chain path reservation. We use simulated annealing to explore possible performance improvements and to motivate the augmented heuristics and their weighting functions. We show that the spatial path scheduling algorithm augmented with these three heuristics achieves a 21% average performance improvement over the best prior algorithm and comes within an average of 5% of the annealed performance for our benchmarks.

A spatial path scheduling algorithm for EDGE architectures

Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE architectures are one example of communication-exposed microarchitectures in which the compiler forms dataflow graphs that specify how the microarchitecture maps instructions onto a distributed execution substrate. This paper describes a compiler scheduling algorithm called spatial path scheduling that factors in previously fixed locations - called anchor points - for each placement. This algorithm extends easily to different spatial topologies. We augment this basic algorithm with three heuristics: (1) local and global ALU and network link contention modeling, (2) global critical path estimates, and (3) dependence chain path reservation. We use simulated annealing to explore possible performance improvements and to motivate the augmented heuristics and their weighting functions. We show that the spatial path scheduling algorithm augmented with these three heuristics achieves a 21% average performance improvement over the best prior algorithm and comes within an average of 5% of the annealed performance for our benchmarks.

Wafer-level package interconnect options

As integrated circuit technology enters the nanometer era, global interconnects are becoming a bottleneck for overall chip performance. In this paper, we show that wafer-level package interconnects are an effective alternative to conventional on-chip global wires. These interconnects behave as LC transmission lines and can be exploited for their near speed of light transmission and low attenuation characteristics. We compare performance measures such as bandwidth, bandwidth density, latency, and power consumption of the package-level transmission lines with conventional on-chip global interconnects for different International Technology Roadmap for Semiconductors (ITRS) technology nodes. Based on these results, we show that package-level interconnects are well suited for power demanding low-latency applications. We also analyze different interconnect options such as memory buses, long inter tile interconnects, clock, and power distribution

Interconnect-Aware Coherence Protocols for Chip Multiprocessors

Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future billion transistor architectures due to their low design complexity, high clock frequency, and high throughput. In a typical CMP architecture, the L2 cache is shared by multiple cores and data coherence is maintained among private L1s. Coherence operations entail frequent communication over global on-chip wires. In future technologies, communication between different L1s will have a significant impact on overall processor performance and power consumption. On-chip wires can be designed to have different latency, bandwidth, and energy properties. Likewise, coherence protocol messages have different latency and bandwidth needs. We propose an interconnect composed of wires with varying latency, bandwidth, and energy characteristics, and advocate intelligently mapping coherence operations to the appropriate wires. In this paper, we present a comprehensive list of techniques that allow coherence protocols to exploit a heterogeneous interconnect and evaluate a subset of these techniques to show their performance and power-efficiency potential. Most of the proposed techniques can be implemented with a minimum complexity overhead.

Pulsed Current-Mode Signaling for Nearly Speed-of-Light Intrachip Communication

In this paper, we describe the design of on-chip repeater-less interconnects with nearly speed-of-light latency. Sharp current-pulse data transmission is used to modulate transmitter energy to higher frequencies, where the effect of wire inductance is maximized, allowing the on-chip wires to function as transmission lines with considerably reduced dispersion. A prototype 8-Gb/s serial link employing this pulsed current-mode signaling in a 0.18-/spl mu/m CMOS process is described and measured.

Crosstalk-Based Capacitance Measurements: Theory and Applications

Geometry scaling increases the relative effect of coupling capacitances on performance, power, and noise so that they need to be carefully taken into account during process development, characterization, and monitoring. In the last decade, charge-based capacitance measurements (CBCMs) have been widely used to estimate on-chip wiring and coupling capacitances because of their accuracy and simplicity. We provide a thorough theoretical and experimental study of CBCMs applied to the selective extraction of cross-coupling capacitances. We take a historical perspective starting from the original CBCM approach proposed by Chen in 1996, and we present a new technique for crosstalk-based capacitance measurements (CTCMs). CTCMs improve the accuracy and usability of CBCMs while reducing the complexity of the test structures. We present the theory of CTCM, we provide experimental results demonstrating its improved accuracy, and we discuss its application to a wide range of process monitoring and testing tasks. Experimental results are used throughout the paper to support the discussion.

Chip-package hybrid clock distribution network and DLL for low jitter clock delivery

This paper presents a chip-package hybrid clock distribution network and delay-locked loop (DLL) with which to achieve extremely low jitter clock delivery. The proposed hybrid clock distribution network and DLL provide digital noise-free and low-jitter clock signals by utilizing lossless package layer interconnections instead of lossy on-chip global wires with cascaded repeaters. The lossless package layer interconnections become high-frequency waveguides and provide a repeater-free clock distribution network; thus, the clock signal becomes free of on-chip power supply noise. The proposed chip-package hybrid clock scheme has demonstrated a 78-ps peak-to-peak jitter at 500 MHz under a 240-mV on-chip simultaneous switching noise condition versus a conventional clock scheme, which produced a 172-ps peak-to-peak jitter under the same condition. Moreover, the proposed scheme has demonstrated an 80-ps long-term jitter with a 300-mV DC voltage drop test condition, contrasted with the 380-ps long-term jitter of a conventional clock scheme. Finally, the proposed hybrid clock scheme has a confirmed delay of 1.47 ns versus a conventional clock scheme delay of 2.85 ns.

A comprehensive performance macro-modeling of on-chip RC interconnects considering line shielding effects

The delay of on-chip interconnect wiring is having an important influence on the timing performance of logic path. This is particularly true where drivers are connected through a non-negligible length of wire. If the Elmore resistance-capacitance delay model remains popular due to its simple formulation, limitations have been shown in sub-micrometer domain due to its inability in capturing input slope and shielding effects. This paper presents an analytical expression for the transition time and the switching delay of an RC interconnect, including the line input and output drivers. Based on a previously developed model of the inverter transition time and the switching delay, we propose a model of the shielding capacitance effect on the input driver. We then determine the transition time of the output driver and the switching delay of the complete structure for different size of input drivers. We validate these analytical expressions with respect to electrical simulations, on 130 and 90 nm processes, using the eldo's transmission line model.

Effects of On-Chip Inductance on Power Distribution Grid

With increase of clock frequency, on-chip wire inductance starts to play an important role in power/ground distribution analysis, although it has not been considered so far. We perform a case study work that evaluates relation between decoupling capacitance position and noise suppression effect, and we reveal that placing decoupling capacitance close to current load is necessary for noise reduction. We experimentally show that impact of on-chip inductance becomes small when on-chip decoupling capacitance is well placed according to local power consumption. We also examine influences of grid pitch, wire area, and spacing between paired power and ground wires on power supply noise. When effect of on-chip inductance on power/ground noise is significant, minification of grid pitch is more efficient than increase in wire area, and small spacing reduces power noise as we expected.

Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI)

In modern-day VLSI systems, performance and manufacturing costs are being driven by the on-chip wiring needs due to the continuous increase in the number of transistors. This paper proposes a low overhead wave-pipelined multiplexed (WPM) routing technique that harnesses the inherent intraclock period interconnect idleness to implement wire sharing throughout the various hierarchical levels of design. It is illustrated in this paper that the WPM network can be readily incorporated into future gigascale integration (GSI) systems to reduce the number of interconnect routing channels in an attempt to contain escalating manufacturing costs. Both, a system level analysis and circuit level verification of this WPM routing are presented in this paper. A multilevel interconnect network design simulator (MINDS) that uses system level interconnect prediction (SLIP) techniques and HSPICE circuit simulations for optimizing the interconnect dimensions has been used to assess the opportunities for application of WPM wire circuits in high performance digital designs. A custom routing example highlights the ease with which the WPM routing technique can be easily incorporated into the existing VLSI systems. In addition, for a 40 million transistor system case study, this system level analysis reveals that the use of a WPM network could result in an almost 20% decrease in the number of metal layers for less than 4% increase in dynamic power with no loss of communication throughput performance. The key virtues of WPM routing are its flexibility, robustness, implementation simplicity and its low overhead requirements.

Comprehensive broad-band electromagnetic modeling of on-chip interconnects with a surface discretization-based generalized PEEC model

A surface integral equation formalism is proposed for broad-band electromagnetic modeling of on-chip signal and power distribution networks. The discrete model is developed in the spirit of the partial element equivalent circuit (PEEC) model, which is extended with several attributes that lead to enhanced modeling versatility, modeling accuracy, and numerical solution robustness from dc to multigigahertz frequencies. Instead of the volumetric discretization model, which has dominated the PEEC-based schemes for handling the tall and slim cross sections of the on-chip wiring, the proposed model relies on a computationally more efficient conductor surface discretization. Key to the effectiveness and accuracy of the proposed surface discretization is the definition of a frequency- and position-dependent impedance quantity on the conductor surface. Its numerical computation over the frequency bandwidth of interest is expedited through the implementation of a complex frequency-hopping algorithm. The resulting effective surface impedance is combined with a mixed triangular/rectangular meshing of the conducting surfaces for the approximation of the surface electric current and charge densities. A systematic strategy for the identification of loops in the resulting discrete model is used to ensure a numerically stable mesh analysis-based PEEC formulation for on-chip signal and power distribution modeling with electromagnetic accuracy from dc to multigigahertz frequencies.

Reboot for the router [IC design

The move to chip designs that use sub-100 nm dimensions is bringing big changes to the tool flows. Magma Design Automation and Synopsys have decided to rewrite their tools to perform physical synthesis, placement and routing because of concerns over the way that on-chip interconnect behaves on 65 nm processes and, to some extent, 90 nm. It is a change that has been coming for a while because on-chip wiring has steadily become a bigger problem since the introduction of the 0.5 μm process more than 10 years ago. Chip-level tool vendors have begun revising their implementation tools as they aim for the upcoming crop of designs for the 65 nm process.

How do carbon nanotubes fit into the semiconductor roadmap?

This paper presents an overview of the issues related to the integration of carbon nanotubes into microelectronics systems. Particular emphasis is placed on the use of carbon nanotubes as on-chip wiring (interconnects) and active devices (transistors), the two main building blocks of current semiconductor circuits. The properties of state-of-the art devices are compared in order to test the viability of replacing silicon-based components with carbon nanotubes. Further, the problems associated with the construction of nanotube-based devices are discussed.

Design and Measurement of an Inductance-Oscillator for Analyzing On-Chip Inductance Impact on Wire Delay

A newly devised inductance-oscillator (iOSC) has been developed which evaluates inductance impact on on-chip wire delay. iOSC is a ring oscillator which is comprised of a set of wires each with different loop inductance and accurate on-chip counter. The equivalent distance to the nearest ground grid, which serves as the current return path, is varied to control wire inductance. A test chip using 0.13-?m node process is fabricated to demonstrate concept of the iOSC. Four wire structures are implemented as imperfect coplanar waveguide, imitating clock lines or high-frequency global signal lines. The structure with largest inductance variation measured 99 ps delay difference while newly proposing twisted ground structure which has small inductance variation measured 6 ps both for 3-mm wires. This experiment also provides designers with a guideline for ground density from inductance standpoint. iOSC confirms that the inductance impact on delay has to be adequately analyzed and controlled to estimate a timing in high-speed LSI designs.

Superfilling and the Curvature Enhanced Accelerator Coverage Mechanism

State-of-the-art manufacturing of semiconductor devices involves the electrodeposition of copper for on-chip wiring of integrated circuits.

Faraday in the Fab: A Look at Copper Plating Equipment for On-Chip Wiring

It has been interesting to watch the growth and development of copper interconnects on silicon chips in the seven years that have passed since IBM announced that it would use electrodeposited copper for the wiring structure of its 0.25-micrometer CMOS7 microprocessor.

SCMP: A Single-Chip Message-Passing Parallel Computer

As technology improves and transistor feature sizes continue to shrink, the effects of on-chip interconnect wire latencies on processor clock speeds will become more important. In addition, as we reach the limits of instruction-level parallelism that can be extracted from application programs, there will be an increased emphasis on thread-level parallelism. To continue to improve performance, computer architects will need to focus on architectures that can efficiently support thread-level parallelism while minimizing the length of on-chip interconnect wires. The SCMP (Single-Chip Message-Passing) parallel computer system is one such architecture. The SCMP system includes up to 64 processors on a single chip, connected in a 2-D mesh with nearest neighbor connections. Memory is included on-chip with the processors and the architecture includes hardware support for communication and the execution of parallel threads. Since there are no global signals or shared resources between the processors, the length of the interconnect wires will be determined by the size of the individual processors, not the size of the entire chip. Avoiding long interconnect wires will allow the use of very high clock frequencies, which, when coupled with the use of multiple processors, will offer tremendous computational power.