Abstract
The move to chip designs that use sub-100 nm dimensions is bringing big changes to the tool flows. Magma Design Automation and Synopsys have decided to rewrite their tools to perform physical synthesis, placement and routing because of concerns over the way that on-chip interconnect behaves on 65 nm processes and, to some extent, 90 nm. It is a change that has been coming for a while because on-chip wiring has steadily become a bigger problem since the introduction of the 0.5 μm process more than 10 years ago. Chip-level tool vendors have begun revising their implementation tools as they aim for the upcoming crop of designs for the 65 nm process.
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