On-chip Transistor Research Articles

Proposal for variability-induced effective radius of elliptical gate-all-around junctionless transistors and its applicability in hydrogen gas sensors

Nano-ribbons with gate-all-around (GAA) architecture have been predicted to serve as next-generation on-chip transistors, among which, the junctionless transistor (JLT) has emerged as a promising candidate, mitigating few limitations of conventional inversion-mode metal–oxide–semiconductor field-effect transistors (MOSFETs). Due to imperfect fabrication process, the GAA architecture is often subject to cross-sectional variabilities. This work presents an analytical model for the effective radius of elliptical cross-section of the channel region having a non-circular oxide surrounding it, resulting in various structural configurations having non-uniform oxide thickness. To demonstrate the impact of cross-sectional variability of GAA-JLTs, few performance parameters, such as, drain current, threshold voltage, and so on, have been evaluated using our proposed formulation for the effective radius and the results were found to agree well with TCAD simulations. As a case study, we have emphasized on the applicability of our proposed model in variability-induced GAA-JLT-based hydrogen sensors using few sensitivity metrics. Our computations show substantial changes in the sensing device as the cross-section deviates from the ideal circular one. Our computations reveal that incorporating the effects of radius variability in the device model along with proper tuning of operating conditions can enhance the performance and accuracy of such sensors.

Fabrication of p-type 2D single-crystalline transistor arrays with Fermi-level-tuned van der Waals semimetal electrodes

High-performance p-type two-dimensional (2D) transistors are fundamental for 2D nanoelectronics. However, the lack of a reliable method for creating high-quality, large-scale p-type 2D semiconductors and a suitable metallization process represents important challenges that need to be addressed for future developments of the field. Here, we report the fabrication of scalable p-type 2D single-crystalline 2H-MoTe2 transistor arrays with Fermi-level-tuned 1T’-phase semimetal contact electrodes. By transforming polycrystalline 1T’-MoTe2 to 2H polymorph via abnormal grain growth, we fabricated 4-inch 2H-MoTe2 wafers with ultra-large single-crystalline domains and spatially-controlled single-crystalline arrays at a low temperature (~500 °C). Furthermore, we demonstrate on-chip transistors by lithographic patterning and layer-by-layer integration of 1T’ semimetals and 2H semiconductors. Work function modulation of 1T’-MoTe2 electrodes was achieved by depositing 3D metal (Au) pads, resulting in minimal contact resistance (~0.7 kΩ·μm) and near-zero Schottky barrier height (~14 meV) of the junction interface, and leading to high on-state current (~7.8 μA/μm) and on/off current ratio (~105) in the 2H-MoTe2 transistors.

Improved noise performance from the next-generation buried-channel p-MOSFET SiSeROs

The Single electron Sensitive Read Out (SiSeRO) is a novel on-chip charge detector output stage for charge-coupled device (CCD) image sensors. Developed at MIT Lincoln Laboratory, this technology uses a p-MOSFET transistor with a depleted internal gate beneath the transistor channel. The transistor source-drain current is modulated by the transfer of charge into the internal gate. At Stanford, we have developed a readout module based on the drain current of the on-chip transistor to characterize the device. In our earlier work, we characterized a number of first prototype SiSeROs with the MOSFET transistor channels at the surface layer. An equivalent noise charge (ENC) of around 15 electrons root mean square (RMS) was obtained. In this work, we examine the first buried-channel SiSeRO. We have achieved substantially improved noise performance of around 4.5 electrons root mean square (RMS) and a full width half maximum (FWHM) energy resolution of 132 eV at 5.9 keV, for a readout speed of 625 kpixel/s. We also discuss how digital filtering techniques can be used to further improve the SiSeRO noise performance. Additional measurements and device simulations will be essential to further mature the SiSeRO technology. This new device class presents an exciting new technology for the next-generation astronomical X-ray telescopes requiring fast, low-noise, radiation-hard megapixel imagers with moderate spectroscopic resolution.

A 90.6% Efficient, 0.333 W/mm2 Power Density Direct 48V-to-1V Dual Inductor Hybrid Converter With Delay-Line-Based V2D Controller

This brief presents a 48V-to-1V 10-level dual inductor hybrid converter (DIHC) containing 11 on-chip switches and an off-chip gallium nitride (GaN) switch. Thanks to the 10-level Dickson switched-capacitor (SC) circuit, most of the voltage stress will be taken over by off-chip capacitors, which reduces the voltage stress of each switch to 4.8 V and takes full advantage of the voltage pressure on the 5-V on-chip transistors. This proposed structure is implemented in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> BCD process to convert 48-V input to 1-V output with up to 18-A current load. The post-layout simulations show that a peak power efficiency of 90.6% can be achieved at 5.2-A loading and the power density is about 0.333 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$W/mm^{2}$ </tex-math></inline-formula> considering the power stage area.

Leveraging On-Chip Transistor Switching for Communication and Sensing in Neural Implants and Gastrointestinal Devices.

This paper presents a Proof-of-Concept (POC) design and implementation of a biosensing and communication system that can be used for biotelemetry in neural and Gastrointestinal (GI) applications. Our proposed system is based on backscattering from a semi-passive Radio-Frequency-Identification-Device (RFID) implemented using an Application Specific Integrated Circuit (ASIC) in which electronic switching between transistor gates in high and low states create an impedance difference, thereby effectively changing the ASIC's Radar Cross Section (RCS) and thus modulating its backscattered field. The ASIC is used in conjunction with a biosensor to measure and transmit vital signs from within the body. With this system, we conducted backscatter propagation experiments through different biological and phantom tissues (in ex-vivo and in-vitro) in the GI and neural environments. Our results show that the backscattered waveforms can penetrate tissues of various compositions and thicknesses with power received at distances of up to 55 cm away from the RFID ASIC. Furthermore, results from single- and multi-bit biotelemetry measurements showed a high signal fidelity with low Bit-Error-Rate (BER) while being able to resolve varying tissue temperatures measured by the biosensor in our system. We realized a POC system in which on-chip transistor switching in an ASIC can be used to achieve backscatter communication and biosensing. This system is deployable in neural and GI applications. Our findings in this work will provide an important practical basis for the design and development of RFID ASIC for biosensing and biotelemetry in medical applications.

Terahertz topological photonics for on-chip communication

The computing speeds in modern multi-core processors and big data servers are no longer limited by the on-chip transistor density that doubles every two years following the Moores law, but are limited by the on-chip data communication between memories and microprocessor cores. Realization of integrated, low-cost, and efficient solutions for high speed, on-chip data communications require terahertz (THz) interconnect waveguides with tremendous significance in future THz technology including THz-wave integrated circuits and THz communication. However, conventional approaches to THz waveguiding suffer from sensitivity to defects and considerable bending losses at sharp bends. Here, building on the recently-discovered topological phase of light, we experimentally demonstrate robust THz topological valley transport on low-loss, all-silicon chips. We show that the valley polarized topological kink states exhibit unity transmission over a bulk band gap even after propagating through ten sharp corners. Such states are excellent information carriers due to their robustness, single-mode propagation, and linear dispersion-key properties for next generation THz communications. By leveraging the unique properties of kink states, we demonstrate error-free communication through a highly-twisted domain wall at an unprecedented data rate (10 Gbit/s) and uncompressed 4K high-definition video transmission. Our work provides the first experimental demonstration of the topological phases of THz wave, which could certainly inspire a plethora of research on different types of topological phases in two and three dimensions.

A High-Speed Si-Based Power Transistor With Bipolar-Assisted Gate Discharging Behavior

This letter presents a novel super junction (SJ) device integrated with an on-chip bipolar junction transistor (BJT) connected between the gate and the source. This parallel path through the BJT to discharge the gate of the SJ device reduces its switch-off time by 26%. It also raises the human-body model electro-static discharge failure threshold from 1.5 to 2.3 kV for the same chip size. In addition, gate voltage oscillation during the switch-off transient is effectively suppressed.

Low-level implementation of the SISC protocol for thread-level speculation on a multi-core architecture

Abstract Chip Multiprocessors (CMP) have emerged during last decades as a very attractive solution in using the ever-increasing on-chip transistor count. However, classical parallelization techniques failed to fully exploit parallelization from existing sequential applications due to false data dependencies. This paper focuses on the Thread-level Speculation (TLS) technique, an alternative way to exploit the transistor budget in a CMP. With TLS, even possibly data dependent threads can run in parallel as long as the semantics of the sequential execution is preserved. A special hardware support monitors the actual data dependencies between threads at run time and, if they are violated, misspeculation effects are undone usually through replay. This kind of system is known as speculative CMP. However, the TLS mechanism requires complex protocols that integrate cache coherence and speculation to maintain program order among multiple versions of data. Current TLS protocol evaluations are usually inadequate because they are not done low-level enough. A realistic evaluation of speculative CMPs requires either to be performed on a real hardware or very detailed cycle-accurate simulator models. In this paper we are particularly focused on a low-level evaluation of the write-invalidate TLS protocol Speculation Integrated with Snoopy Coherence (SISC) protocol proposed in [1] . This evaluation relies on cycle-level simulation environment with detailed cycle-level cache memories, cache controller and system bus. On top of this, a speculative four core architecture is simulated and three new modules (Scheduler, Squash Arbiter and Supplier Arbiter) are provided to support low-level implementation of the SISC protocol. The overall cost of the SISC protocol is evaluated by means of CACTI tool for the three different domains: the access latency cost, the area cost, and the power cost. The evaluation goal was to keep the cache access time to remain below cycle latency as well as the area and power overheads below an acceptable budget overhead. The SISC protocol has been compared against regular MESI-based architecture in both 32-bit and 64-bit versions. We kept the cache access time below the cycle latency, and we managed to keep both data cache area and static power overheads respectively below 32% and 35%.

FDSOI and Bulk CMOS SRAM Cell Resilience to Radiation Effects

With shrinking dimensions and increased number of on-chip transistors radiation can provoke faults in integrated circuits even at sea level. This paper presents a comparison of fully depleted SOI (FDSOI) and Bulk CMOS 6T SRAM cells' resilience to radiation effects. Both cells were simulated using TCAD tools, considering heavy-ion impacts in different locations of the transistor as well as using different impact angles. Two types of radiation effects have been considered: Single-Event Transients (SETs) and Single-Event Upsets (SEUs). The minimum critical collected charge (CC) to flip a cell is almost the same in both technologies. However, it is shown that a FDSOI SRAM cell needs a heavy-ion impact with a Linear Energy Transfer (LET) around 10 times greater than a Bulk-CMOS SRAM cell, to generate a similar CC and to flip a cell.

(Invited) Role of Interfaces in Achieving Self-Compliance Controlled Resistive Random Access Memory Devices for Low-Power Embedded Applications

Resistive Random Access Memory (ReRAM) devices are considered promising candidates for emerging Non-Volatile Memory (NVM) applications. ReRAM devices can be switched at very low voltages using ultra-fast pulses. In addition, these devices can be easily integrated in Complementary Metal Oxide Semiconductor (CMOS) process-flow due to simplistic configuration, materials and process compatibility. These properties make them attractive for not only stand-alone off-chip memory applications but also for low-power embedded memory applications. However, there are several challenges that need to be addressed to take the complete benefit of this enabling technology. For example, currently available ReRAM devices suffer from variability and limited endurance. Additionally, these devices need a careful control of current, referred to as compliance current (CC), during electroforming and set operations which is typically achieved using a current limiting circuitry or an on-chip transistor. A tight control of CC is needed to control the filament dimension during forming and set operations of ReRAM to prevent the permanent breakdown of the device. However, the necessity of current limiting circuitry or transistor makes the integration of ReRAM devices in crossbar architectures difficult in 1Diode-1ReRAM (1D1R) configuration using bidirectional diodes as selector devices. Therefore, there is an urgent need to develop ReRAM devices which are self-compliance current (SCC) controlled where no additional current limiting circuitry or transistor is needed to limit the current through the device. This paper will discuss the role of interfacial layer (IL) engineering between electrodes and switching oxides towards achieving SCC ReRAM devices. Experimental results will be presented to show routes to scale down the switching currents in SCC ReRAM devices via the control of compositions and thicknesses of IL. Device performance parameters including endurance, retention, and reliability characteristics of these devices will be discussed. Finally, mechanism behind SCC and device models will be discussed which can be used for circuit level simulations.

Improvements in Light-Load Efficiency and Operation Frequency for Low-Voltage Current-Mode Integrated Boost Converters

This brief presents design techniques to improve both the power efficiency and the operation frequency of low-voltage current-mode boost converters for single-cell NiMH battery applications. For delivering a wide range of load currents, a cross-conduction-free width-switching (CCF-WS) technique is developed to eliminate the short-circuit power loss associated with switching different segments of on-chip power transistors, thereby improving the converter light-load power efficiency. A low-voltage current sensor is also proposed to increase the sensing speed. Hence, the converter operation frequency is improved and the required value of the inductor in the power stage is reduced. A boost converter was implemented in a standard 0.35-μm CMOS process. The converter can accept a minimum input voltage of 1.2 V, deliver a maximum output current of 200 mA, and properly operate at a switching frequency of 1 MHz with only a small inductor of 4.7 μH. The proposed boost converter increases the switching frequency by at least 3.3 times compared with the previously reported low-voltage designs. The converter also achieves a maximum power efficiency of 90% and provides up to 11.5% power efficiency improvement with the CCF-WS technique.

Prevention from Soft Errors via Architecture Elasticity

Due to the decreasing threshold voltages, shrinking feature size, as well as the exponential growth of on-chip transistors, modern processors are increasingly vulnerable to soft errors. However, traditional mechanisms of soft error mitigation take actions to deal with soft errors only after they have been detected. Instead of the passive responses, this paper proposes a novel mechanism which proactively prevents from the occurrence of soft errors via architecture elasticity. In the light of a predictive model, we adapt the processor architectures holistically and dynamically. The predictive model provides the ability to quickly and accurately predict the simulation target across different program execution phases on any architecture configurations by leveraging an artificial neural network model. Experimental results on SPEC CPU 2000 benchmarks show that our method inherently reduces the soft error rate by 33.2% and improves the energy efficiency by 18.3% as compared with the static configuration processor.

THE FREQUENCY BEHAVIOUR OF THE INTRINSIC IMMUNITY OF THE ON-CHIP TRANSISTOR CIRCUIT

To extract the immunity model in an easy way and to complete the immunity simulation in a short time, it is preferred to consider only the disturbance propagation network in an integrated circuit system. However, through theoretical analyses, simulations and measurements, this paper shows that the on-chip transistor circuit has a nonuniform frequency response on its immunity against arrival disturbances. Including the nonuniform frequency response qualitatively improves the match between the simulation and measurement results. The conclusion is that both the disturbance propagation network and on-chip transistor circuit should be considered in the immunity simulation. The evaluation of the electrical performance in the design phase of an electronic system can only be conducted with simulation. Simulating the radio frequency (RF) immunity of integrated circuits (ICs) is interesting in the design phase of the ICs and printed circuit boards. IEC has established a standard for immunity modelling of ICs (1). The frequency of the RF interference (RFI) signal is labeled with fRFI. The RF immunity of ICs is characterized with immunity curves in fRFI range from below 1MHz to near or above 1GHz. The immunity curve shows, for each fRFI, the maximal RFI power (PRFI T) that the IC can tolerate. Normally, a measured RF immunity has the frequency behaviour that PRFI T varies strongly with fRFI. The main task of the RF immunity modeling is to simulate that frequency behaviour. When a RFI signal is applied to an IC, the signal goes through the disturbance propagation network (DPN) and arrives at the on-chip transistor circuit (OCTC). Previous researches (2{7) in immunity modeling of modern ICs have focused on constructing the model of DPN and use the frequency behaviour of DPN to reproduce the frequency behaviour of the RF immunity. However, besides DPN, the response of OCTC to the arrived RFI may vary with fRFI. The relationship between the maximal tolerable RFI voltage which has arrived at OCTC and fRFI is called the intrinsic immunity of OCTC. The motivation of this paper is to check whether the intrinsic immunity of OCTC is, in fRFI range from 1MHz to 1GHz, a constant or not. If the intrinsic immunity is a constant, then modeling the DPN is su-cient to simulate the RF immunity of the IC. Otherwise, the frequency behaviour of the intrinsic immunity of OCTC should be included in simulating the RF immunity of the IC. The latter will complicate the immunity modeling to a greater degree, because simulating a modern IC, no matter the whole chip or a functional module, at transistor level normally requires huge resources. The \Frequency Behaviour of the Immunity section analyses the signal relations in the immunity test flxture, and explains the concepts of immunity and intrinsic immunity. The \simulation section illustrates two approaches of the immunity simulation. One approach considers the intrinsic immunity of OCTC while the other does not. The \Discussion section compares the simulation results with the measurement results. The difierence in the results of the two approaches brings out the conclusion on the importance of the intrinsic immunity.

Effect of Ti doping and annealing on multi-level forming-free resistive random access memories with atomic layer deposited HfTiOx nanolaminate

HighlightsWe demonstrated forming-free switching using atomic layer deposited HfTiOx nanolaminate.Effect of Hf:Ti ratio and anneal conditions on switching characteristics were studied.Multi-level operation with four distinct levels and stable retention were observed. In this work, we investigate the effects of the Hf:Ti ratio and annealing temperature on the properties of forming-free resistive memories with atomic layer deposited (ALD) HfTiOx nano-laminate. Devices with 25% Ti doping (Hf:Ti=3:1) in the dielectric show reliable forming-free switching while 50% Ti doped samples (Hf:Ti=1:1) remain conducting at all applied voltages. No significant effect of annealing was observed on the switching characteristics of the devices. The forming-free devices show capability to operate without any external or on-chip transistor and exhibit multi-level capability with four distinct levels and stable retention for all the levels.

Introduction to the CHES 2012 special issue

The 14th International Workshop on Cryptographic Hardware and Embedded Systems (CHES 2012) was held at the Katholieke Universiteit Leuven, Belgium, during September 9–12, 2012. This special issue presents expanded versions of 5 of the best ranked papers from the CHES Workshop. The CHES Workshop covers new results on all aspects of the design and analysis of cryptographic hardware and software implementations. The workshop builds a bridge between the cryptographic research community and the cryptographic engineering community. Since its inception in 1999, CHES has grown into the flagship event for the cryptographic engineering community. In this special issue, you will find 5 of the best ranked papers among the 120 submissions received by theworkshop. These papers were identified based on the review scores of the CHES review process, and the expanded journal submissions of these papers received an additional, independent peer-review. The five papers in this special issue reflect the broad spectrum of topics that is typically found in a CHES workshop and include physical hardware security, novel hardware architectures, and novel implementation attacks using faults and side-channel analysis. The first paper, “Simple Photonic Emission Analysis of AES”, is by Alexander Schlosser, Dmitry Nedospasov, Juliane Kramer, Susanna Orlic, and Jean-Pierre Seifert. The authors describe how direct optical observation of on-chip transistor switching enables sidechannel analysis. The second paper, “On the Use of Physical

High-Performance Energy-Efficient Multicore Embedded Computing

With Moore's law supplying billions of transistors on-chip, embedded systems are undergoing a transition from single-core to multicore to exploit this high-transistor density for high performance. Embedded systems differ from traditional high-performance supercomputers in that power is a first-order constraint for embedded systems; whereas, performance is the major benchmark for supercomputers. The increase in on-chip transistor density exacerbates power/thermal issues in embedded systems, which necessitates novel hardware/software power/thermal management techniques to meet the ever-increasing high-performance embedded computing demands in an energy-efficient manner. This paper outlines typical requirements of embedded applications and discusses state-of-the-art hardware/software high-performance energy-efficient embedded computing (HPEEC) techniques that help meeting these requirements. We also discuss modern multicore processors that leverage these HPEEC techniques to deliver high performance per watt. Finally, we present design challenges and future research directions for HPEEC system development.

Fast Electromagnetics-Based Co-Simulation of Linear Network and Nonlinear Circuits for the Analysis of High-Speed Integrated Circuits

A fast electromagnetic simulator is developed to co-simulate the linear network and nonlinear circuits in an integrated circuit system. In this simulator, the physical layout of a large-scale linear network is rigorously reduced to a single surface or a few surfaces where the nonlinear circuits are located. The reduction is done analytically, and, hence, the computational overhead is minimal. The reduced system is then split into a linear system and a nonlinear system so that both systems can be solved efficiently. The linear system of equations is solved rapidly by the time-domain layered finite-element reduction-recovery method. The nonlinear system of equations is solved by developing an efficient method. This method renders the contribution from the linear network to the nonlinear system a diagonal matrix in the Jacobian matrix, hence significantly speeding up the nonlinear solution. After the reduced system is solved, the unknowns elsewhere in the computational domain are recovered efficiently by the time-domain layered finite-element reduction-recovery method. The proposed simulator has been applied to co-simulate on-chip interconnects and CMOS transistors. Numerical results have demonstrated its accuracy and efficiency. The proposed simulator is capable of capturing the global electrical interaction between integrated circuit interconnects, package, RF/analog components, substrates, and nonlinear drivers/receivers across the full electromagnetic spectrum. In addition, it bypasses the extraction of the linear network, preserves the passivity and stability of the linear network, and captures the interaction between the linear network and nonlinear devices.

Characterization of Fixed and Reconfigurable Multi-Core Devices for Application Acceleration

As on-chip transistor counts increase, the computing landscape has shifted to multi- and many-core devices. Computational accelerators have adopted this trend by incorporating both fixed and reconfigurable many-core and multi-core devices. As more, disparate devices enter the market, there is an increasing need for concepts, terminology, and classification techniques to understand the device tradeoffs. Additionally, computational performance, memory performance, and power metrics are needed to objectively compare devices. These metrics will assist application scientists in selecting the appropriate device early in the development cycle. This article presents a hierarchical taxonomy of computing devices, concepts and terminology describing reconfigurability, and computational density and internal memory bandwidth metrics to compare devices.

Challenges and opportunities at all levels

The tremendous advances in process technology have opened the doors to many opportunities, but have also introduced a wealth of challenges. On one hand, microprocessor designers can pack several cores, whether homogeneous or heterogeneous, on a single chip, enabling more parallelism. On the other hand, programmers must focus on producing parallel programs since automatic parallelization is still in its infancy, especially for non-scientific code. System designers must also focus on managing resources to optimize performance and minimize the impact on power and reliability. The increase in on-chip transistors results in increased power dissipation, both static and dynamic, and gives rise to other challenges related to parameter variations. The main question facing the entire computing community is how to make use of all the available cores in the most efficient and cost-effective way. This challenge can be addressed by changing the way multicore processors, compilers, and operating systems interact. This interaction is the main topic of this special issue.

Reducing Area Overhead for Error-Protecting Large L2/L3 Caches

Due to increasing concern about various errors, current processors adopt error protection mechanisms for their on-chip components. Especially, protecting caches in current processors incurs as much as 12.5 percent area overhead due to error-correcting codes (ECCs). Considering large L2/L3 caches employed in current high-performance processors, the area overhead is very high, consuming a large number of on-chip transistors. As an attempt to reduce that overhead, this paper proposes an area-efficient error protection architecture for large L2/L3 caches. First, it selectively applies ECC to only dirty cache lines, and other clean cache lines are protected by using simple parity check codes. Second, the dirty cache lines are periodically cleaned by exploiting the generational behavior of cache lines in order not to increase traffic to the off-chip main memory. Experimental results show that the cleaning technique effectively reduces the average number of dirty cache lines per cycle. The ECCs of the reduced dirty cache lines can be confined in a small ECC array or ECC cache. Our proposed error protection architecture has been shown to reduce the area overhead of a 1-Mbyte L2 cache for error protection by 59 percent with less than 1 percent performance degradation, on the average, using SPEC2000 benchmarks running on a typical four-issue superscalar processor. A dirty cache line cleaning scheme is also beneficial for reducing the vulnerability of tag arrays to soft errors.