On-chip Temperature Research Articles

All optical reconfiguration of optomechanical filters

Reconfigurable optical filters are of great importance for applications in optical communication and information processing. Of particular interest are tuning techniques that take advantage of mechanical deformation of the devices, as they offer wider tuning range. Here we demonstrate reconfiguration of coupled photonic crystal nanobeam cavities by using optical gradient force induced mechanical actuation. Propagating waveguide modes that exist over a wide wavelength range are used to actuate the structures and control the resonance of localized cavity modes. Using this all-optical approach, more than 18 linewidths of tuning range is demonstrated. Using an on-chip temperature self-referencing method, we determine that 20% of the total tuning was due to optomechanical reconfiguration and the rest due to thermo-optic effects. By operating the device at frequencies higher than the thermal cutoff, we show high-speed operation dominated by just optomechanical effects. Independent control of mechanical and optical resonances of our structures is also demonstrated.

A Systematic Methodology for Reliability Improvements on SoC‐Based Software Defined Radio Systems

Shrinking silicon technologies, increasing logic densities and clock frequencies, lead to a rapid elevation in power density. Increased power density results in higher onchip temperature, which creates numerous problems tightly firmed to reliability degradation. Since typical low‐power design has been proved inefficient to tackle the temperature increment by itself, device architects are facing the challenge of developing new methodologies to guarantee timing, power, and thermal integrity of the chip. In this paper, we propose a thermal‐aware exploration framework targeting temperature hotspots elimination through the efficient exploration of multiple microarchitecture selections over the temperature‐area trade‐off curve. By carefully planning at design time the resources of the initial microarchitecture that should be replicated, the proposed methodology optimizes the system’s thermal profile and attens on‐chip temperature under various design constraints. The introduced framework does not impose any architectural or compiler modification, whereas it is orthogonal to any other thermal‐aware methodology. For evaluation purposes, we employ the software‐defined radio executed onto a thermal‐aware instance of LEON3 processor. Based on experimental results, we found that our methodology leads to an architecture that exhibits temperature reduction of 17 Kelvin degrees, which leads to improvement against aging phenomena about 14%, with a controllable overhead in silicon area about 15%, compared to the initial LEON3 instance.

A Multifrequency Passive Sensing Tag With On-Chip Temperature Sensor and Off-Chip Sensor Interface Using EPC HF and UHF RFID Technology

State-of-the-art passive RFID tags are limited in terms of functionality and operating range due to the limited power that can be converted from the electromagnetic field. This is why state-of-the-art wireless sensor systems are mostly battery-based if a high operating range is required. The proposed ultralow-power on-chip sensor unit and off-chip sensor interface which provides enough energy to supply various sensors with a power consumption up to the milliwatt range make it possible to remotely power the proposed RFID tag and use it as wireless sensor node. Equipping sensor nodes with RFID functionality not only enables identification and logistic applications but also an easy integration of the sensing tag into existing RFID systems. Exploiting the different characteristics of HF and UHF RFID systems, namely the large operating range in UHF and the high available power in HF, increases the flexibility and applicability of wireless sensor nodes. This paper presents a remotely powered multifrequency sensing tag according to the EPC HF and EPC Class 1 Gen 2 UHF standard developed in a 0.13- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu$</tex></formula> m low-cost CMOS process. Input powers of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}$</tex></formula> 10.3 or <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}$</tex></formula> 7.9 dBm at a frequency of 900 MHz are necessary to operate the sensing tag with activated on-chip sensor unit or off-chip sensor interface, respectively.

Combined TiN- and TaN temperature compensated thin film resistors

The opposite signs of the temperature coefficient of resistance (TCR) of two thin film materials, titanium nitride (TiN) and tantalum nitride (TaN), were used to form temperature compensated thin film resistors (TFRs). The principle of designing temperature compensated TFRs by connecting TFRs of each compound in series or in parallel was demonstrated. TiN, TaN, and combined TiN and TaN TFRs for monolithic microwave integrated circuits (MMICs) were fabricated by reactive sputtering. DC characterization was performed over the temperature range of 30–200 °C. The TiN TFRs exhibited an increase in resistivity with temperature with TCRs of 540 and 750 ppm/°C. The TaN TFR on the other hand exhibited a negative TCR of − 470 ppm/°C. The shunted TFRs were fabricated by serial deposition of TiN and TaN to form a bilayer component. The TCRs of the series- and shunt configurations were experimentally reduced to − 60 and 100 ppm/°C, respectively. The concept of temperature compensation was used to build a Wheatstone bridge with an application in on-chip temperature sensing.

Time-Bounded Authentication of FPGAs

This paper introduces a novel technique to authenticate and identify field-programmable gate arrays (FPGAs). The technique uses the reconfigurability feature of FPGAs to perform self-characterization and extract the unique timing of the FPGA building blocks over the space of possible inputs. The characterization circuit is then exploited for constructing a physically unclonable function (PUF). The PUF can accept different forms of challenges including pulsewidth, digital binary, and placement challenges. The responses from the PUF are only verifiable by entities with access to the unique timing signature. However, the authentic device is the only entity who can respond within a given time constraint. The constraint is set by the gap between the speed of PUF evaluation on authentic hardware and simulation of its behavior. A suite of authentication protocols is introduced based on the time-bounded mechanism. We ensure that the responses are robust to fluctuations in operational conditions such as temperature and voltage variations by employing: 1) a linear calibration mechanism that adjusts the clock frequency by a feedback from on-chip temperature and voltage sensor readings, and 2) a differential PUF structure with real-valued responses that cancels out the common impact of variations on delays. Security against various attacks is discussed and a proof-of-concept implementation of signature extraction and authentication are demonstrated on Xilinx Virtex 5 FPGAs.

An Electro-Magnetic Energy Harvesting System With 190 nW Idle Mode Power Consumption for a BAW Based Wireless Sensor Node

State-of-the-art wireless sensor nodes are mostly supplied by batteries. Such systems have the disadvantage that they are not maintenance free because of the limited lifetime of batteries. Instead, wireless sensor nodes or related devices can be remotely powered. To increase the operating range and applicability of these remotely powered devices an electro-magnetic energy harvester iPs developed in a 0.13 μ m low cost CMOS technology. This paper presents an energy harvesting system that converts RF power to DC power to supply wireless sensor nodes, active transmitters or related systems with a power consumption up to the mW range. This energy harvesting system is used to power a wireless sensor node from the 900 MHz RF field. The wireless sensor node includes an on-chip temperature sensor and a bulk acoustic wave (BAW) based transmitter. The BAW resonator reduces the startup time of the transmitter to about 2 μs which reduces the amount of energy needed in one transmission cycle. The maximum output power of the transmitter is 5.4 dBm. The chip contains an ultra-low-power control unit and consumes only 190 nW in idle mode. The required input power is -19.7 dBm.

Thermal Sensing With Lithographically Patterned Bimetallic Thin-Film Thermocouples

A chromium-nickel thin-film thermocouple that is 50 nm thick is demonstrated on a semiconductor substrate as proof of concept for lithographically processed bimetallic on-chip temperature sensors. The Seebeck coefficient of the thin-film thermocouple is calibrated to be 10.37 μV/°C, reproducibly smaller than the bulk literature value by a factor of 3.98. The batch reproducibility of this thin-film Seebeck coefficient is demonstrated. The linear Seebeck response up to 90°C is calibrated with the help of a simple formula which accounts for the temperature variations of the reference thermocouple under large heat loads.

Sensitivity Improvement of Biosensors Using Si Ring Optical Resonators

We have been demonstrating label-free detection of a variety of antigen–antibody reactions using Si ring optical resonators. Although the detection of biomarkers for the diagnosis of diseases generally requires high sensitivity of the order of 10-9 g/ml, the detection sensitivity of our device is currently of the order of 10-6 g/ml. In this paper, we show that the sensitivity of 10-9 g/ml will be possible by adopting the following four strategies: (1) use of slot-type waveguides with light wavelength of 1.3 µm, (2) improvement of quality factor Q of the ring resonator by smoothing the surface roughness, (3) specific adsorption of the bioreceptor protein to the resonator surface, and (4) maintaining temperature within ±0.005 °C. We have also proposed the on-chip temperature compensation method without the need for temperature control of the sample. By combining the proposed approaches, the sensitivity of the biosensor will be improved by a factor of >100, thus realizing practical application of our Si ring biosensor.

Sensitivity Improvement of Biosensors Using Si Ring Optical Resonators

We have been demonstrating label-free detection of a variety of antigen–antibody reactions using Si ring optical resonators. Although the detection of biomarkers for the diagnosis of diseases generally requires high sensitivity of the order of 10-9 g/ml, the detection sensitivity of our device is currently of the order of 10-6 g/ml. In this paper, we show that the sensitivity of 10-9 g/ml will be possible by adopting the following four strategies: (1) use of slot-type waveguides with light wavelength of 1.3 µm, (2) improvement of quality factor Q of the ring resonator by smoothing the surface roughness, (3) specific adsorption of the bioreceptor protein to the resonator surface, and (4) maintaining temperature within ±0.005 °C. We have also proposed the on-chip temperature compensation method without the need for temperature control of the sample. By combining the proposed approaches, the sensitivity of the biosensor will be improved by a factor of >100, thus realizing practical application of our Si ring biosensor.

A Wireless Sensor Node Supporting Various Powers Supply and Communication Methods

Problem statement: This study presents a wireless sensor node dedicated for in-tire pressure and temperature monitoring. Additional features set it apart from the many different systems available on the highly competitive market. State-of-the-art implementations are mounted on the rim of a tire. Here the sensor node will be mounted on the inner liner of the tire. By moving the sensor node from the rim to the inner liner, new challenges in the analog design arise. Approach: To implement this sensor node new power supply methods are investigated. Next, analog designs with the focus on low power are developed. Since the sensor node is operated in a harsh environment, robustness is a key issue. Results: The discussed sensor is capable of either active or passive communication. The passive communication is used in the field of Radio Frequency Identification (RFID), whereas active communication is used to transmit the sensor data. A combination of both is also possible. To supply the chip in the tire an RF energy harvesting interface is implemented. An input sensitivity of -19.7dBm for the harvesting interface and -12.5 dBm for the RFID interface is measured. The on-chip temperature sensor consumes 4μA including the analog to digital converter. Conclusion: Choosing the discussed sensor node for in-tire monitoring enables new fields of applications. With this sensor node sensing additional parameters like road condition is possible. Using passive communication improves warehouse management for tire manufactures. Also, tire type identification at the car is enabled.

Electrothermal Design Procedure to Observe RF Circuit Power and Linearity Characteristics With a Homodyne Differential Temperature Sensor

The focus in this paper is on the extraction of RF circuit performance characteristics from the dc output of an on-chip temperature sensor. Any RF input signal can be applied to excite the circuit under examination because only dissipated power levels are measured, which makes this approach attractive for online thermal monitoring and built-in test scenarios. A fully differential sensor topology is introduced that has been specifically designed for the proposed method by constructing it with a wide dynamic range, programmable sensitivity to dc, and RF power dissipation, as well as compatibility with CMOS technology. This paper also presents an outline of a procedure to model the local electrothermal coupling between heat sources and the sensor, which is used to define the temperature sensor's specifications as well as to predict the thermal signature of the circuit under test. A prototype chip with an RF amplifier and temperature sensor was fabricated in a conventional 0.18-μm CMOS technology. The proposed concepts were validated by correlating RF measurements at 1 GHz with the measured dc voltage output of the on-chip sensor and the simulation results, demonstrating that the RF power dissipation can be monitored and the 1-dB compression point can be estimated with less than 1-dB error. The sensor circuitry occupies a die area of 0.012 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , which can be shared when several on-chip locations are observed by placement of multiple temperature-sensing parasitic bipolar devices.

An on-chip temperature compensation circuit for an InGaP/GaAs HBT RF power amplifier

A new on-chip temperature compensation circuit for a GaAs-based HBT RF amplifier applied to wireless communication is presented. The simple compensation circuit is composed of one GaAs HBT and five resistors with various values, which allow the power amplifier to achieve better thermal characteristics with a little degradation in performance. It effectively compensates for the temperature variation of the gain and the output power of the power amplifier by regulating the base quiescent bias current. The temperature compensation circuit is applied to a 3-stage integrated power amplifier for wireless communication applications, which results in an improvement in the gain variation from 4.0 to 1.1 dB in the temperature range between −20 and +80 °C.

Unified datacenter power management considering on-chip and air temperature constraints

The current approaches for datacenter power management focus primarily on maintaining the air temperature surrounding servers to be within the manufacturer specified constraint. This is problematic since several CPUs may still be violating the on-chip thermal constraint thereby leading to reliability loss. The primary objective of this work is to develop a unified approach for datacenter power optimization (by controlling the CPU speeds) which accounts for both the silicon level temperature of the VLSI components such as CPUs and the air temperature that directly impacts the reliability of other devices such as disks, and also the performance delivered. Our algorithm follows a two step approach: optimally solving a convex approximation that assigns continuous frequency values to all CPUs and a discretization step for legalization of the assigned frequencies. The experimental results indicate that our method guarantees both on-chip CPU and off-chip air temperature to be within temperature constraints. However, the traditional approach of constraining only on air temperature will result in on-chip CPU temperature violation in about 40% of the CPUs, or 42% more power consumption to pull the CPU temperature back within constraint by increasing the air conditioner cooling.

Cyber-Physical Thermal Management of 3D Multi-Core Cache-Processor System with Microfluidic Cooling

Existing three-dimensional (3D) integration of multi-core processor-cache system is confronted with the problem of die thermal run-away hazard. This teething problem is addressed by a real-time demand-based thermal management with non-uniform microfluidic cooling in this paper. A novel runtime temperature management is implemented to predict the real-time temperature demand based on software-sensing with prediction-and-correction. A 3D thermal model is developed to cater the real-time microfluidic thermal dynamics. An autoregressive (AR) prediction with correction is implemented by Kalman filtering to predict and correct the runtime power, which is further used to calculate the future temperature demand. With this software-sensing approach, thermal management can be performed in a cyber-physical fashion with real-time sensing, prediction-and-correction and fine-grained control. Compared to the existing works using on-chip temperature sensors, our closed-loop controller with software-sensing avoids the cost of sensor implementation and deployment. Our work analyzes and predicts the fine-grained temperature profile of multi-core processor-cache system. It enables a number of microfluidic channels to be adjusted adaptively with different flow-rates to control the system temperature proactively as opposed to the static control with a uniform flow-rate for microfluidic channels. With the proposed cyber-physical temperature management scheme, it is shown that the temperature of multi-core system is suppressed below an acceptable thermal threshold. In fact, the fine-grained flow-rate control also achieves a more even temperature distribution and saves up to 72.1% of total flow-rate compared with uniform flow-rate controls.

Simultaneous Characterization of Theta-JC and Theta-JB Using Through-Package 1-D Heat Flow

A new technique is proposed for simultaneous, in-situ characterization of in-package thermal resistances (junction-to-case and junction-to-board) in a single test. A thin resistive heater is patterned on package top surface to establish one-dimensional heat conduction along the package vertical direction. Accompanying temperature rise at the heater is measured using a thermocouple and analyzed to estimate equivalent thermal R-C network model of the package. Due to the one-dimensionality of the probing thermal wave, the derived R-C network model represents physical package thermal structure, enabling simultaneous estimation of both thermal resistances (theta-JC and theta-JB). The proposed technique is validated by measuring theta-JC and JB of an overmolded flip-chip ball grid array package. The proposed method eliminates need for a separate test setup for the characterization of each thermal resistance, enhancing the accuracy and efficiency of the package thermal characterization. In addition, use of the external heater and sensing element, instead of on-chip heater and temperature sensor, enables in-situ thermal characterization of a real package mounted on the set board.

A microfluidic approach for investigating the temperature dependence of biomolecular activity with single-molecule resolution.

We present a microfluidic approach for single-molecule studies of the temperature-dependent behavior of biomolecules, using a platform that combines microfluidic sample handling, on-chip temperature control, and total internal reflection fluorescence (TIRF) microscopy of surface-immobilized biomolecules. With efficient, rapid, and uniform heating by microheaters and in situ temperature measurements within a microfluidic flowcell by micro temperature sensors, closed-loop, accurate temperature control is achieved. To demonstrate its utility, the temperature-controlled microfluidic flowcell is coupled to a prism-based TIRF microscope and is used to investigate the temperature-dependence of ribosome and transfer RNA (tRNA) structural dynamics that are required for the rapid and precise translocation of tRNAs through the ribosome during protein synthesis. Our studies reveal that the previously characterized, thermally activated transitions between two global conformational states of the pre-translocation (PRE) ribosomal complex persist at physiological temperature. In addition, the temperature-dependence of the rates of transition between these two global conformational states of the PRE complex reveal well-defined, measurable, and disproportionate effects, providing a robust experimental framework for investigating the thermodynamic activation parameters that underlie transitions across these barriers.

On-Chip Temperature Compensation Active Bias Circuit Having Tunable Temperature Slope for GaAs FET MMIC PA

On-Chip Temperature Compensation Active Bias Circuit Having Tunable Temperature Slope for GaAs FET MMIC PA

A Thermal-Diffusivity-Based Frequency Reference in Standard CMOS With an Absolute Inaccuracy of $\pm $0.1% From $-$55 $^{\circ}$C to 125 $^{\circ}$C

An on-chip frequency reference exploiting the well-defined thermal-diffusivity (TD) of IC-grade silicon has been realized in a standard 0.7 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\mu{\hbox{m}}$</tex></formula> CMOS process. A frequency-locked loop (FLL) locks the frequency of a digitally controlled oscillator (DCO) to the process-insensitive phase shift of an electrothermal filter (ETF). The ETF's phase shift is determined by its geometry and by the thermal diffusivity of bulk silicon ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$D$</tex> </formula> ). The temperature dependence of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$D$</tex></formula> is compensated for with the help of die-temperature information obtained by an on-chip band-gap temperature sensor. The resulting TD frequency reference has a nominal output frequency of 1.6 MHz and dissipates 7.8 mW from a 5 V supply. Measurements on 16 devices show that it has an absolute inaccuracy of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\pm $</tex></formula> 0.1% ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\sigma= \pm $</tex></formula> 0.05%) over the military temperature range ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex></formula> 55 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$^{\circ}{\hbox{C}}$</tex></formula> to 125 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$^{\circ}{\hbox{C}}$</tex></formula> ), with a worst case temperature coefficient of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\pm \hbox{11.2~ppm}/^{\circ}{\hbox{C}}$</tex></formula> .

A System-on-Chip EPC Gen-2 Passive UHF RFID Tag With Embedded Temperature Sensor

This paper presents a system-on-chip passive RFID tag with an embedded temperature sensor for the EPC Gen-2 protocol in the 900-MHz UHF frequency band. A dual-path clock generator is proposed to support both applications with either very accurate link frequency or very low power consumption. On-chip temperature sensing is accomplished with a time-readout scheme to reduce the power consumption. Moreover, a gain-compensation technique is proposed to reduce the temperature sensing error due to process variations by using the same bandgap reference of the tag to generate bias currents for both the current-to-digital converter and the clock generator of the sensor. Also integrated is a 128-bit one-time-programmable (OTP) memory array based on gate-oxide antifuse without extra mask steps. Fabricated in a standard 0.18- μm CMOS process with analog options, the 1.1-mm2 tag chip is bonded onto an antenna using flip-chip technology to realize a complete tag inlay, which is successfully demonstrated and evaluated in real-time wireless communications with commercial RFID readers. The tag inlay achieves a sensitivity of -6 dBm and a sensing inaccuracy of ±0.8° C (3 σ inaccuracy) over operating temperature range from -20°C to 30°C with one-point calibration.

Thermal-Aware Clock Tree Design to Increase Timing Reliability of Embedded SoCs

Chip heating and nonuniform distribution of hot and cool zones on the die negatively affect reliability and robustness to failures of nanometer integrated circuits. In fact, signal propagation on interconnects slows down as temperature rises; for long wires crossing regions at different temperatures, such as the clock network, thermally induced delay and skew get altered and may result in timing faults. Failures of this kind are difficult to face due to their transient nature. This paper focuses on clock tree design for the class of embedded systems-on-chip with spatially nonuniform but temporally stationary thermal profiles. We contribute two algorithms for the thermal-aware clock network design that take into account on-chip temperature variations of this nature. The experimental results that we have collected on a number of examples and for different thermal profiles show that, in the presence of on-chip spatial temperature gradients, clock trees designed using a standard methodology incur very significant skew violations, thus originating circuit failures. Instead, clock networks designed using the algorithms presented in this paper always satisfy the initial skew bound.