On-chip Temperature Research Articles

An efficient method for analyzing on-chip thermal reliability considering process variations

This work provides an efficient statistical electrothermal simulator for analyzing on-chip thermal reliability under process variations. Using the collocation-based statistical modeling technique, first, the statistical interpolation polynomial for on-chip temperature distribution can be obtained by performing deterministic electrothermal simulation very few times and by utilizing polynomial interpolation. After that, the proposed simulator not only provides the mean and standard deviation profiles of on-chip temperature distribution, but also innovates the concept of thermal yield profile to statistically characterize the on-chip temperature distribution more precisely, and builds an efficient technique for estimating this figure of merit. Moreover, a mixed-mesh strategy is presented to further enhance the efficiency of the developed statistical electrothermal simulator. Experimental results demonstrate that (1) the developed statistical electrothermal simulator can obtain accurate approximations with orders of magnitude speedup over the Monte Carlo method; (2) comparing with a well-known cumulative distribution function estimation method, APEX [Li et al. 2004], the developed statistical electrothermal simulator can achieve 215× speedup with better accuracy; (3) the developed mixed-mesh strategy can achieve an order of magnitude faster over our baseline algorithm and still maintain an acceptable accuracy level.

Whispering-gallery mode composite sensors for on-chip dynamic temperature monitoring

Whispering-gallery mode temperature microsensors have been demonstrated to have extremely high accuracy. Previous experiments have been limited to indirect sensor heating by externally heating the local environment. In this paper, we coated PDMS films directly onto an electrical resistive wire as sensors, allowing on-chip dynamic temperature measurement. The effects of sensor size are discussed and verified through an expansion of the current theory of WGM resonance shifts to include composite materials. Finally, the WGM sensor's measurements are compared to the same measurements recorded by a thermocouple, demonstrating the great advantages of WGM sensors for on-chip real temperature monitoring.

On-Chip Process and Temperature Monitor for Self-Adjusting Slew Rate Control of 2$\,\times\,$VDD Output Buffers

A novel process and temperature compensation design for 2 VDD output buffers is proposed, where the threshold voltages (Vth) of PMOSs and NMOSs varying with process and temperature deviation could be detected, respectively. A prototype 2 × VDD output buffer using the proposed compensation design is fabricated using a typical 0.18 μm CMOS process. By adjusting output currents, the slew rate of output signals could be compensated over 117%. The maximum data rate with compensation is 120 MHz in contrast with 95 MHz without compensation, which is measured on silicon with an equivalent probe capacitive load of 10 pF.

A Subthreshold-MOSFETs-Based Scattered Relative Temperature Sensor Front-End With a Non-Calibrated $\pm 2.5^{\circ}{\rm C}$$3\sigma$ Relative Inaccuracy From -$40^{\circ}{\rm C}$ to 100$^{\circ}{\rm C}$

This paper presents a subthreshold MOSFETs-based scattered relative temperature sensor front-end operating at a low supply voltage. Dynamic element matching and dynamic offset cancellation have been implemented to minimize the errors induced by device mismatches. An individual proportional-to-absolute-temperature (PTAT) voltage generator was first implemented to verify the low voltage operation capability and the mismatch-error correction. A low voltage reference circuit has been also designed and tested. A gate-bulk-driven error correction amplifier is proposed in order to minimize the offset error and maintain low voltage operation. The scattered relative temperature sensor front-end was then implemented in AMI 0.5 μm CMOS process with an array of 5 × 5 sensor nodes across the chip. The minimum supply voltage was measured as 1 V over -40-100°C with a typical N-JP-type threshold voltage of around 0.8 V and 0.9 V at room temperature, respectively. The measured relative inaccuracy was less than ±2.5°C without calibration. To the best of the authors' knowledge, this is the first time that non-calibrated on-chip relative temperature monitoring accuracy is reported. Furthermore, the multi-location thermal monitoring function has been experimentally demonstrated and a 2°C/mm on-chip temperature gradient was detected.

Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization

With the continuing scaling of CMOS technology, on-chip temperature and thermal-induced variations have become a major design concern. To effectively limit the high temperature in a chip equipped with a cost-effective cooling system, thermal specific approaches, besides low power techniques, are necessary at the chip design level. The high temperature in hotspots and large thermal gradients are caused by the high local power density and the nonuniform power dissipation across the chip. With the objective of reducing power density in hotspots, we propose two placement techniques that spread cells in hotspots over a larger area. Increasing the area occupied by the hotspot directly reduces its power density, leading to a reduction in peak temperature and thermal gradient. To minimize the introduced overhead in delay and dynamic power, we maintain the relative positions of the coupling cells in the new layout. We compare the proposed methods in terms of temperature reduction, timing, and area overhead to the baseline method, which enlarges the circuit area uniformly. The experimental results showed that our methods achieve a larger reduction in both peak temperature and thermal gradient than the baseline method. The baseline method, although reducing peak temperature in most cases, has little impact on thermal gradient.

High-throughput, energy-efficient network-on-chip-based hardware accelerators

Several emerging application domains in scientific computing demand high computation throughputs to achieve terascale or higher performance. Dedicated centers hosting scientific computing tools on a few high-end servers could rely on hardware accelerator co-processors that contain multiple lightweight custom cores interconnected through an on-chip network. With increasing workloads, these many-core platforms need to deliver high overall computation throughput while also being energy-efficient. Conventional multicore architectures can achieve a limited computational throughput due to the inherent multi-hop nature of the on-chip network infrastructure. By inserting long-range links that act as shortcuts in a regular network-on-chip (NoC) architecture, both the achievable bandwidth and energy efficiency of a multicore platform can be significantly enhanced. In this paper, we first propose a NoC-driven use-case model for throughput-oriented scientific applications, and subsequently use the model to study the effect of using long-range links in conjunction with different resource allocation strategies on reducing the overall on-chip communication and enhancing computational throughput. NoCs with both wired and on-chip wireless links are explored in the study. We also evaluate our NoC-based platforms with respect to energy-efficiency and power consumption. We analyze how throughput and power consumption are correlated with the statistical properties of the application traffic. In addition, we compare and analyze chip-level thermal profiles for these alternatives. Our experiments using kernels from a popular phylogenetic inference application suite show that we can deliver computation throughput over 1011 operations per second, consuming ∼0.5nJ per operation, while ensuring that on-chip temperature variation is within 26°C.

Real-time and on-chip surface temperature sensing of GaN LED chips using PbSe quantum dots

PbSe quantum dots (QDs) were employed as real-time and on-chip temperature sensors to monitor the surface temperature of GaN LED chips. The temperature-dependent photoluminescence spectra were achieved and confirmed to be a good method for surface temperature sensing in a micro- to nano-region. The nanosized QD sensors did not influence the LED emission spectrum due to their infrared emission and little absorption. The surface temperature of GaN LED chips was analyzed at different working times and voltages. The temperature sensitivity characterized by the photoluminescence peak position of PbSe QDs was found to be 0.15 nm °C(-1) in a range of 30-120 °C and the precision was determined to be ± 3 °C. The QD surface temperature sensors were confirmed to have good reversibility and repeatability.

On‐chip temperature compensation for optical transmitter modules

On-chip temperature compensation (TC) for optical transmitter (Tx) modules is reported. The TC block is integrated in common silicon (Si)-substrate with the Tx and demonstrates the ability to maintain a constant VCSEL output light power without an additional monitoring photodiode. Designed and fabricated in a 0.13 µm technology, the Tx with a TC block operates at up to 5 Gbit/s. A BER of less than 10− 12 is achieved at a received input power of − 3 dBm, with a 1.3 dBm variation of received power for a temperature increase of 20–100°C at 5 Gbit/s data rate. The percentage error of the temperature compensated Tx output light power is ± 3%. The Tx module consumes a power of 20 mW at 1.3 V, including the TC block.

A Noise Source Module for In-Situ Noise Figure Measurements From DC to 50 GHz at Cryogenic Temperatures

This letter presents the design and performance of a noise source module for in-situ noise temperature measurements at cryogenic temperatures. The noise source module operates from DC up to 50 GHz and is suitable for measurements of noise temperatures as low as a few Kelvin, achieving a measurement accuracy of about $\pm {1.2}~{\rm K}$ . The GaAs MMIC used in the module includes a well matched 50 $\Omega$ termination with better than 20 dB return loss, a heating element and an on-chip temperature sensor, hence the noise source module can directly be connected to the device under test (DUT) with no additional elements or transitions needed. The measurement can then be taken with standard noise measurement equipment. Noise temperatures as low as 13 K have been measured in Ka-band with this device. Due to the ease of use, the good matching, the extraordinary bandwidth and the less involved calibration technique, the noise source module outperforms the conventional measurement setup using a noise diode in conjunction with a cooled attenuator.

Performance Analysis of Temperature Management Approaches in Networks-on-Chip

With the progress of deep submicron technology, power consumption and temperature related issues have become dominant factors for chip design. Therefore, very large-scale integrated systems like Systems-on-Chip (SoCs) are exposed to an increasing thermal stress. On the one hand, this necessitates effective mechanisms for thermal management. On the other hand, application of thermal management is accompanied by disturbance of system integrity and degradation of system performance. In this paper the authors propose to precompute and proactively manage on-chip temperature of systems based on Networks-on-Chip (NoCs). Thereby, traditional reactive approaches, utilizing the NoC infrastructure to perform thermal management, can be replaced. This results not only in shorter response times for application of management measures and a reduction of temperature and thermal imbalances, but also in less impairment of system integrity and performance. The systematic analysis of simulations conducted for NoC sizes ranging from 2x2 to 4x4 proves that under certain conditions the proactive approach is able to mitigate the negative impact of thermal management on system performance while still improving the on-chip temperature profile.

A 200 °C Universal Gate Driver Integrated Circuit for Extreme Environment Applications

High-temperature power converters (dc-dc, dc-ac, etc.) have enormous potential in extreme environment applications, including automotive, aerospace, geothermal, nuclear, and well logging. For successful realization of such high-temperature power conversion modules, the associated control electronics also need to perform at high temperature. This paper presents a silicon-on-insulator (SOI) based high-temperature gate driver integrated circuit (IC) incorporating an on-chip low-power temperature sensor and demonstrating an improved peak output current drive over our previously reported work. This driver IC has been primarily designed for automotive applications, where the underhood temperature can reach 200 °C. This new gate driver prototype has been designed and implemented in a 0.8 μm, 2-poly, and 3-metal bipolar CMOS-DMOS (Double-Diffused Metal-Oxide Semiconductor) on SOI process and has been successfully tested for up to 200 °C ambient temperature driving a SiC MOSFET and a SiC normally-ON JFET. The salient feature of the proposed universal gate driver is its ability to drive power switches over a wide range of gate turn-ON voltages such as MOSFET (0 to 20 V), normally-OFF JFET (-7 to 3 V), and normally-ON JFET (-20 to 0 V). The measured peak output current capability of the driver is around 5 A and is thus capable of driving several power switches connected in parallel. An ultralow-power on-chip temperature supervisory circuit has also been integrated into the die to safeguard the driver circuit against excessive die temperature (≥220 °C). This approach utilizes increased diode leakage current at higher temperature to monitor the die temperature. The power consumption of the proposed temperature sensor circuit is below 10 μW for operating temperature up to 200 °C.

An On-Chip Temperature Sensor With a Self-Discharging Diode in 32-nm SOI CMOS

We report a 39 μm × 27 μm on-chip temperature sensor which uses the temperature-dependent reverse-bias leakage current of a lateral silicon on insulator (SOI) CMOS p-n diode to monitor the thermal profile of a 32-nm microprocessor core. In this sensor, the diode junction capacitance is first charged to a fixed voltage. Subsequently, the diode capacitance is allowed to self-discharge through its temperature-dependent reverse-bias current. Next, by using a time-to-digital-converter circuit, the discharge voltage is converted to a temperature-dependent time pulse, and finally, its width is measured by using a digital counter. This compact temperature sensor demonstrates a 3σ measurement inaccuracy of ±1.95°C across the 5°C-100°C temperature range while consuming only 100 μW from a single 1.65-V supply.

All-CMOS low supply voltage scattered thermal monitoring front-end

Presented is a low-voltage all-CMOS scattered thermal monitoring architecture front-end designed in a 0.5 µm process. To support low-voltage operation for scaled CMOS technologies, MOSFETs operating in the subthreshold region and an amplifier with a bulk-driven technique are used. To reduce the offset error caused by device mismatches, gain boosting, dynamic offset cancellation and dynamic element matching methods are adopted. The sensor node occupies an area of 90×70 µm2. The measured minimum supply voltage was 1.1 V over a −55 to 125 °C temperature range. The front-end was chamber tested and the performances are reported. Experiments demonstrated the multi-corner thermal monitor detecting on-chip temperature gradients from 1.2 to 26 °C/mm.

TCEC: Temperature and Energy-Constrained Scheduling in Real-Time Multitasking Systems

The ongoing scaling of semiconductor technology is causing severe increase of on-chip power density and temperature in microprocessors. This urgently requires both power and thermal management during system design. In this paper, we propose a model checking-based technique using extended timed automata to solve the processor frequency assignment problem in a temperature and energy-constrained multitasking system. We also develop a polynomial time-approximation algorithm to address the state-space explosion problem caused by symbolic model checker. Our approximation scheme is guaranteed to not generate any false-positive answer, while it may return false-negative answer in rare cases. Our method is universally applicable since it is independent of any system and task characteristics. Experimental results demonstrate the usefulness of our approach.

Electrospun Nanofibrous Membranes for Temperature Regulation of Microfluidic Seed Growth Chips

This paper reports a simple and effective approach to control statistical pore size distributions within electrospun nanofibrous membranes (ENMs), by choosing appropriate spinning times of electro-spinning deposition. Mean pore diameter of ENMs decreases exponentially with increasing spinning time. This pore-size control method is demonstrated to regulate amount of heat energy reaching microfluidic seed growth chips (SGC) and thus growth temperature of seeds on the chips, without using sophisticated semiconductor manufacturing techniques or additional on-chip electronic circuits. Decreasing mean pore diameter of ENMs causes to decrease the on-chip temperature, following a second-order polynomial trend. Phenotypic study based on real-time observation of root architecture is conducted on multiple SGCs under various temperature conditions obtained by using ENMs with different pore size distributions.

A Low Power Real-time On-Chip Power Sensor in 45-nm SOI

This paper introduces a real-time on-chip power and temperature sensor for active power management in scaled CMOS technologies. In a distinct departure from earlier power estimation techniques, this sensor measures the voltage drop due to a current load and converts it into pulse counts to get a power estimate in real time. Linear regression is used to estimate load current based on the measured output frequency at a given temperature. The same sensor is also used to estimate temperature in a mode where output time period decreases linearly with temperature. Measurement results show accuracy to within ±1.05 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C for temperature estimation in the range of 22 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C-100 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C and within ±10% of the actual power consumed (for loads ≤ 3.3 mA). Fabricated in 45-nm SOI technology, this power and temperature sensor occupies an area of 140 μm×140μm and has a power overhead of 120 μW at 1.2 V supply.

Two-Port Static Coated Micro Gas Chromatography Column With an Embedded Thermal Conductivity Detector

This paper reports a microfabricated 2×4 cm gas chromatography chip to separate and detect gases in a two-port structure by embedding a microthermal conductivity detector (μTCD) within a separation column. A circular on-chip heater is placed on the backside of the monolithic device enabling temperature programming and consequently faster analysis of the heavier components. A unique process enhanced by reactive ion etching lag (RIE lag) is used to achieve multiple etch depths in silicon and restrict the process flow to just three masks. The silicon substrate contains the separation column, the heater, and the tunnels for the TCD electric feed throughs. A Pyrex wafer containing the TCD elements is anodically bonded to the silicon substrate to seal the structure. Performance of a standalone μTCD fabricated in the same process and integrated in a hybrid fashion is also described. The single-chip design demonstrates successful separation and identification of multi-component gas mixtures with a performance comparable to that obtained through a flame ionization detector connected in series. Further, on-chip temperature programming capability was utilized to elevate the column temperature to 75 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C to exhibit analysis in less than a minute.

Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs

With the leakage-thermal dependency, the increasing on-chip temperature in 3D designs has serious impact on IR drop due to the increased wire resistance and increased leakage current. Therefore, it is necessary to consider Power/Ground network design with thermal effects in 3D designs. Though Power/Ground (P/G) TSV can help to relieve the IR drop violation by vertically connecting on-chip P/G networks on different layers, most previous work restricts the uniform P/G grids so that the potential of P/G TSV planning has not been fully explored. In this paper, we present an efficient thermal-aware P/G TSV planning algorithm based on a sensitivity model with temperature-dependent leakage current considered. Non-uniform P/G grid topology is explored to optimize the P/G network by allowing short wires to connect the P/G TSVs to P/G grids. Both the theoretical analysis and experimental results show the efficiency of our approach. Results show that neglecting thermal impacts on power delivery can underestimate IR drop by about 11%. To relieve the severe IR drop violation, 51.8% more P/G TSVs are needed than the cases without thermal impacts considered. Results also show that our P/G TSV planning based on the sensitivity model can reduce max IR drop by 42.3% and reduce the number of violated nodes by 82.4%.

Temperature-modulated differential scanning calorimetry in a MEMS device

We present a MEMS-based approach to temperature-modulated differential scanning calorimetry (AC-DSC) for biomolecular characterization. Based on a MEMS device integrating microfluidic handling with highly sensitive thermoelectric detection as well as on-chip AC heating and temperature sensing, we perform, for the first time, MEMS-based AC-DSC detection of liquid biological samples, demonstrated by the measurements of protein unfolding. The specific heat capacity and the melting temperature of the protein during the unfolding process are obtained and found to be consistent with published data. This MEMS AC-DSC approach has potential applications to label-free characterization of biomolecules.

Analysis and On-Chip Monitoring of Gate Oxide Breakdown in SRAM Cells

Scaling of device sizes has reduced gate oxide thickness to a few atomic layers, increasing the vulnerability of the gate oxide to breakdown. During breakdown, devices go through a gradual wearout process characterized by increased leakage. Using experimentally verified gate oxide breakdown models, a detailed analysis of the effect of progressive gate oxide breakdown on the performance of a conventional 6T SRAM cell is presented for 45-nm predictive technology. The DC margins (read, write, and retention) and access times (read and write) during wearout are analyzed, and a cell breakdown point due to degradation in each of these parameters is defined. A combination of these results is used to formulate a definition for the hard-breakdown point of a cell. An on-chip process, voltage, and temperature tolerant monitoring scheme is proposed to detect the gradual wearout of SRAM cells. The monitoring scheme enables the detection of impending cell failure, which in turn can trigger reconfiguration of the SRAM with redundant rows and/or columns prior to failure.