On-chip Resource Utilization Research Articles

AMROFloor: An Efficient Aging Mitigation and Resource Optimization Floorplanner for Virtual Coarse-Grained Runtime Reconfigurable FPGAs

With the rapid reduction of CMOS process size, the FPGAs with high-silicon accumulation technology are becoming more sensitive to aging effects. This reduces the reliability and service life of the device. The offline aging-aware layout planning based on balance stress is an effective solution. However, the existing methods need to take a long time to solve the floorplanner, and the corresponding layout solutions occupy many on-chip resources. To this end, we proposed an efficient Aging Mitigation and Resource Optimization Floorplanner (AMROFloor) for FPGAs. First, the layout solution is implemented on the Virtual Coarse-Grained Runtime Reconfigurable Architecture, which contributes to avoiding rule constraints for placement and routing. Second, the Maximize Reconfigurable Regions Algorithm (MRRA) is proposed to quickly determine the RRs’ number and size to save the solving time and ensure an effective solution. Furthermore, the Resource Combination Algorithm (RCA) is proposed to optimize the on-chip resources, reducing the on-Chip Resource Utilization (CRU) while achieving the same aging relief effect. Experiments were simulated and implemented on Xilinx FPGA. The results demonstrate that the AMROFloor method designed in this paper can extend the Mean Time to Failure (MTTF) by 13.8% and optimize the resource overhead by 19.2% on average compared to the existing aging-aware layout solutions.

Hardware-efficient implementation and experimental demonstration of Hermitian-symmetric IFFT for optical DMT transmitter.

Optical discrete multi-tone (DMT) is one type of direct-detection optical orthogonal frequency-division multiplexing (DDO-OFDM), and it is more suitable for cost-sensitive access networks and optical interconnections due to its simple structure. In DMT transmitter, inverse fast Fourier transform (IFFT) is an essential function for achieving OFDM modulation, and its input data are constrained to have Hermitian symmetry (HS). To support high-speed DMT signal generation, a fully-parallel implementation of IFFT is preferable. However, the hardware implementation of the conventional complex-valued IFFT (CC-IFFT) requires large area and has high power consumption. Based on the nature of HS, we design and implement a fully-parallel pipelined 128-point radix-2 decimation-in-time Hermitian-symmetric IFFT (HS-IFFT) by using a single field programmable gate array (FPGA) chip. On-chip resource utilization is analyzed for both the proposed HS-IFFT and CC-IFFT. It exhibits that the HS-IFFT can save up to 35% multipliers, 49% registers and 43% look-up tables (LUTs) compared to the CC-IFFT. Also, by using the HS-IFFT and CC-IFFT, two FPGA-based real-time baseband DMT transmitters are implemented and power consumption is estimated. More than 32% of on-chip power is saved by using the HS-IFFT. Moreover, the two DMT transmitters are also experimentally demonstrated in a short-reach directly-modulated laser (DML)-based optical DMT system. The experimental results show that the HS-IFFT-DMT has the same bit error rate (BER) and error vector magnitude (EVM) performances as the CC-IFFT-DMT in both electrical/optical back-to-back cases (EB2B/OB2B) and post 20-km single-mode fiber (SMF) transmission.

Efficient separable convolution using field programmable gate arrays

Two-dimensional (2D) convolution is an essential component in several image and video processing applications. The convolution operation is computationally expensive due to the large number of required additions and multiplications. Field Programmable Gate Array (FPGA) architectures have been used to mitigate this problem owing to their parallel processing capabilities. Using separable filter kernels can further improve the convolution operation both in terms of resource utilization and speed. Although several 2D convolution implementations have been presented in the literature, research on separable convolution using FPGA is limited.This paper presents a new separable FPGA-based convolution architecture. The goal is to reduce both on-chip resource utilization and external memory bandwidth for a given processing rate of the convolution unit. External memory bandwidth (EMB) and on-chip resource utilization are reduced by reusing common data shared by consecutive processing windows in a novel way. Comparisons with existing separable convolution methods demonstrate improvements offered by the proposed technique in terms of on-chip resource utilization and power consumption.

Dynamic application allocation with resource balancing on NoC based many-core embedded systems

Abstract It is a fundamental challenge to manage on-chip resources for future embedded applications executing concurrently on a NoC (network on chip) based many-core embedded system (MES). Embedded application allocation is required under constraints in the form of computing resources or communication resources. However, most existing techniques only focus on the optimization of communications between application threads and ignore a balanced utilization of on-chip resources, which is critical for embedded systems. In this paper, we propose a dynamic resource balance (DRB) algorithm to achieve a higher system performance by balancing the utilization of on-chip computing resources and communication resources. The DRB algorithm first constructs a mapping scheme using a dynamic communication optimization (DCO) algorithm and then chooses a corresponding number of resource regions for the constructed mapping scheme to allocate the application using a multi-rectangle selection (MRS) algorithm. We evaluate DRB algorithm in a popular simulator Graphite whose results reveal that DRB algorithm improves system throughput by at most up to 31.6%, 25.2%, and 9.4% compared with FF (First Free) algorithm, NN (Nearest Neighbor) algorithm, and CoNA-SHiC (Contiguous Neighbor Allocation and Smart Hill Climbing) algorithm, respectively.

A Configurable Architecture for Sparse LU Decomposition on Matrices with Arbitrary Patterns

Sparse LU decomposition has been widely used to solve sparse linear systems of equations found in many scientific and engineering applications, such as circuit simulation, power system modeling and computer vision. However, it is considered a computationally expensive factorization tool. While parallel implementations have been explored to accelerate sparse LU decomposition, irregular sparsity patterns often limit their performance gains. Prior FPGA-based accelerators have been customized to domain-specific sparsity patterns of pre-ordered symmetric matrices. In this paper, we present an efficient architecture for sparse LU decomposition that supports both symmetric and asymmetric sparse matrices with arbitrary sparsity patterns. The control structure of our architecture parallelizes computation and pivoting operations. Also, on-chip resource utilization is configured based on properties of the matrices being processed. Our experimental results show a 1:6 to 14x speedup over an optimized software implementation for benchmarks containing a wide range of sparsity patterns.

A shared matrix unit for a chip multi-core processor

This paper proposes extending a multi-core processor with a common matrix unit to maximize on-chip resource utilization and to leverage the advantages of the current multi-core revolution to improve the performance of data-parallel applications. Each core fetches scalar/vector/matrix instructions from its instruction cache. Scalar instructions continue the execution on the scalar datapath; however, vector/matrix instructions are issued by the decode stage to the shared matrix unit through the corresponding FIFO queue. Moreover, scalar results from reduction vector/matrix instructions are sent back from the matrix unit to the scalar core that sent these instructions. Some dense linear algebra kernels (scalar–vector multiplication, scalar times vector plus another, apply Givens rotation, rank-1 update, vector–matrix multiplication, and matrix–matrix multiplication) as well as discrete cosine transform, sum of absolute differences, and affine transformation are used in the performance evaluation. Our results show that the improvement in the utilization of the shared matrix unit with a dual-core ranges from 9% to 26% compared to extending a matrix unit to a single-core. Moreover, the average speedup of the dual-core shared matrix unit over a single-core extended with a matrix unit ranges from 6% to 24% and the maximum speedup ranges from 13% to 46%.

Godson-T: An Efficient Many-Core Processor Exploring Thread-Level Parallelism

Godson-T is a research many-core processor designed for parallel scientific computing that delivers efficient performance and flexible programmability simultaneously. It also has many features to achieve high efficiency for on-chip resource utilization, such as a region-based cache coherence protocol, data transfer agents, and hardware-supported synchronization mechanisms. Finally, it also features a highly efficient runtime system, a Pthreads-like programming model, and versatile parallel libraries, which make this many-core design flexibly programmable.

Atomic Streaming: A Framework of On-Chip Data Supply System for Task-Parallel MPSoCs

State of the art fabrication technology for integrating numerous hardware resources such as Processors/DSPs and memory arrays into a single chip enables the emergence of Multiprocessor System-on-Chip (MPSoC). Stream programming paradigm based on MPSoC is highly efficient for single functionality scenario due to its dedicated and predictable data supply system. However, when memory traffic is heavily shared among parallel tasks in applications with multiple interrelated functionalities, performance suffers through task interferences and shared memory congestions which lead to poor parallel speedups and memory bandwidth utilizations. This paper proposes a framework of stream processing based on-chip data supply system for task-parallel MPSoCs. In this framework, stream address generations and data computations are decoupled and parallelized to allow full utilization of on-chip resources. Task granularities are dynamically tuned to jointly optimize the overall application performance. Experiments show that proposed framework as well as the tuning scheme are effective for joint optimization in task-parallel MPSoCs.

A Dynamically Self-reconfigurable System Design Based on SSE Instruction Set

The Dynamic Reconfiguration Technology provides powerful technological support to achieve high-performance general-purpose CPU system in resolving the application of diversity issues, meanwhile improving the enhanced on-chip resource utilization, reducing the complexity of the design, cost and power consumption. The dissertation designs the integer part of the Intel SSE Instruction Set computing Reduced Instruction Set Computer CPU (RISC_CPU) and dynamically self-reconfigurable DISC_CPU, combining the Dynamic Reconfiguration Technology with the general-purpose CPU technology, and achieves Dynamic Instruction Set Computer CPU (DISC_CPU) supporting for multiple SSE (Streaming SIMD Extensions) Instruction Set on a single-chip FPGA.

Godson-T: An Efficient Many-Core Architecture for Parallel Program Executions

Moore’s law will grant computer architects ever more transistors for the foreseeable future, and the challenge is how to use them to deliver efficient performance and flexible programmability. We propose a many-core architecture, Godson-T, to attack this challenge. On the one hand, Godson-T features a region-based cache coherence protocol, asynchronous data transfer agents and hardware-supported synchronization mechanisms, to provide full potential for the high efficiency of the on-chip resource utilization. On the other hand, Godson-T features a highly efficient runtime system, a Pthreads-like programming model, and versatile parallel libraries, which make this many-core design flexibly programmable. This hardware/software cooperating design methodology bridges the high-end computing with mass programmers. Experimental evaluations are conducted on a cycle-accurate simulator of Godson-T. The results show that the proposed architecture has good scalability, fast synchronization, high computational efficiency, and flexible programmability.

A Multiwindow Partial Buffering Scheme for FPGA-Based 2-D Convolvers

Two-dimensional (2-D) convolution is widely used in image and video processing. Although the operation is simple, 2-D convolution is however both computationally expensive and memory-intensive. Field-programmable-gate-array (FPGA)-based parallel processing architectures were proposed to accelerate calculations for 2-D convolution. And data buffers implemented with FPGA on-chip resources were used to avoid direct access to external memories. Full buffering and partial buffering (PB) schemes were adopted in previous works. The former would consume a large amount of FPGA resources, while the latter would cause a sharp increase in external memory bus bandwidth. In this brief, we present a multiwindow PB scheme for FPGA-based 2-D convolvers. Compared with the aforementioned methods, the new buffering strategy exhibits a good balance between on-chip resource utilization and external memory bus bandwidth, and therefore is suitable for low-cost FPGA implementation