A Dynamically Self-reconfigurable System Design Based on SSE Instruction Set

Abstract

The Dynamic Reconfiguration Technology provides powerful technological support to achieve high-performance general-purpose CPU system in resolving the application of diversity issues, meanwhile improving the enhanced on-chip resource utilization, reducing the complexity of the design, cost and power consumption. The dissertation designs the integer part of the Intel SSE Instruction Set computing Reduced Instruction Set Computer CPU (RISC_CPU) and dynamically self-reconfigurable DISC_CPU, combining the Dynamic Reconfiguration Technology with the general-purpose CPU technology, and achieves Dynamic Instruction Set Computer CPU (DISC_CPU) supporting for multiple SSE (Streaming SIMD Extensions) Instruction Set on a single-chip FPGA.