Abstract
With the rapid reduction of CMOS process size, the FPGAs with high-silicon accumulation technology are becoming more sensitive to aging effects. This reduces the reliability and service life of the device. The offline aging-aware layout planning based on balance stress is an effective solution. However, the existing methods need to take a long time to solve the floorplanner, and the corresponding layout solutions occupy many on-chip resources. To this end, we proposed an efficient Aging Mitigation and Resource Optimization Floorplanner (AMROFloor) for FPGAs. First, the layout solution is implemented on the Virtual Coarse-Grained Runtime Reconfigurable Architecture, which contributes to avoiding rule constraints for placement and routing. Second, the Maximize Reconfigurable Regions Algorithm (MRRA) is proposed to quickly determine the RRs’ number and size to save the solving time and ensure an effective solution. Furthermore, the Resource Combination Algorithm (RCA) is proposed to optimize the on-chip resources, reducing the on-Chip Resource Utilization (CRU) while achieving the same aging relief effect. Experiments were simulated and implemented on Xilinx FPGA. The results demonstrate that the AMROFloor method designed in this paper can extend the Mean Time to Failure (MTTF) by 13.8% and optimize the resource overhead by 19.2% on average compared to the existing aging-aware layout solutions.
Highlights
Field Programmable Gate Array (FPGA) is a highly integrated semi-custom electrical device with the characteristics of high parallelism, low power consumption, and fast calculation speed
homogeneous minimize makespan (Hom_MS): The layout solution with homogeneous RRs aims at minimizing the makespan of the tasks; heterogeneous shortest makespan (Het_MS): The layout solution with heterogeneous RRs aims at minimizing the makespan of the tasks; Hom_AM: The layout solution with homogeneous RRs aims at aging mitigation; heterogeneous aging mitigation (Het_AM): The layout solution with heterogeneous RRs aims at aging mitigation; random layout (RL): Random layout solution
It can be seen that the Mean Time to Failure (MTTF) of the aging-aware layout solutions is significantly better than the MS and RL with the increase of total resources
Summary
Field Programmable Gate Array (FPGA) is a highly integrated semi-custom electrical device with the characteristics of high parallelism, low power consumption, and fast calculation speed. The experiments argue the possibility of optimizing resources by changing the layout solution while ensuring the same effects of aging mitigation These issues above open the possibility of achieving FPGA aging mitigation and resource optimization based on heterogeneous RRs. To avoid the restrictions of placement and routing rules on layout heterogeneous RRs, our research aims to introduce aging mitigation in heterogeneous RRs based on FPGA overlays. We should quickly determine the appropriate number and size of RRs to reduce the solving time and optimize the issue of the existing layout planning occupying too many on-chip resources. A Resource Combination Algorithm (RCA) is proposed to further optimize the resources of the layout planning that has achieved aging mitigation; Experimental results show that the AMROFloor method can extend the Mean Time to Failure (MTTF) of FPGAs by 13.8% and optimize the resource overhead by 19.2%.
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