Abstract
Coarse-Grained Reconfigurable Architectures (CGRA) is an effective solution for speeding up computer-intensive activities due to its high energy efficiency and flexibility sacrifices. The timely implementation of CGRA loops was one of the hardest problems in the analysis. Modulo scheduling (MS) was productive in order to implement loops on CGRAs. The problem remains with current MS algorithms, namely to map large and irregular circuits to CGRAs over a fair period of compilation with restricted computational and high-performance routing tools. This is mainly due to an absence of awareness of major mapping limits and a time consuming approach to solving temporary and space-related mapping using CGRA buffer tools. It aims to boost the performance and robust compilation of the CGRA modulo planning algorithm. The problem with the CGRA MS is divided into time and space and the mechanisms between the two problems have to be reorganized. We have a detailed, systematic mapping fluid that addresses the algorithms of the time mapping problem with a powerful buffer algorithm and efficient connection and calculation limitations. We create a fast-stable algorithm for spatial mapping with a retransmission and rearrangement mechanism. With higher performance and quicker build-up time, our MS algorithm can map loops to CBGRA. The results show that, given the same compilation budget, our mapping algorithm results in a better rate for compilation. The performance of this method will be increased from 5% to 14%, better than the standard CGRA mapping algorithms available.
Highlights
Coarse-Grained Reconfigurable Architectures (CGRA) have become an important subject for academia and industry in recent years
The compiler which was extracted from the software application in this generalized CGRA prototype can formulate a consistent Data Flow Graph (DFG) problem and its map ping object is subject to the CGRA execution scheme
This paper sums up the contribution as follows: 1. We examine current CGRA algorithms of mapping and suggest a mapping theory breaking down space and time charts
Summary
CGRA have become an important subject for academia and industry in recent years. Our consciousness reveals that at least 40 CGRAs have been engineered to accommodate various applications in recent decades. Compilers use modular CGRA loops that have proven to be an NP mapping problem. (5) The current mapping rules like EPIMap[17], REGIMap, Conflict-free[18], MemAware and RAMP should be included in space-map ping buffering, PE placement as well as space maps They formulate a problem of spatial mapping that is an NP concern. 2. In time-mapping we cause a buffer allocation problem by setting restrictions and rules for the different buffer sources and assigning routing paths to optimise the issued device resources according to their respective restrictions and rules. In comparison with advanced CGRA Mapping algorithms, our mapping processes increase the efficiency of successfully mapped loops from 5.4% to 14.2% and the build time between.
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