On-chip Power Grid Research Articles

GridNetOpt: Fast Full-Chip EM-Aware Power Grid Optimization Accelerated by Deep Neural Networks

This article presents a fast full-chip electromigration (EM) aware IR drop constrained optimization framework, named GridNetOpt, for on-chip power grid networks accelerated by deep neural networks (DNN). Compared to the existing linear programming-based methods, the new method employs more flexible conjugate gradient-based optimization to size the wire width of the power grids. To mitigate the high cost of sensitivity calculation of the adjoint network using full-chip IR drop analysis at every iteration step, the sensitivity is computed via a trained conditional generative adversarial network (CGAN). The new method exploits the differentiable characteristics of DNNs for fast sensitivity computation. The sensitivity, which is the node voltage with respect to wire resistance, will guide the search direction during the optimization process. In order to consider more accurate EM failure effects, the training data is obtained from the power grids under different wire widths and current loads analyzed by a state-of-the-art full-chip multi-physics-based coupled EM-IR drop analysis tool. This is in contrast with the existing linear programming-based methods, in which only immortal wires or wires with non-zero resistance can be dealt with. Numerical results on a number of synthesized power grid benchmarks from ARM Cortex-M0 processor designs show that the proposed GridNetOpt can lead to at least an order of magnitude speedup over the conjugate gradient-based method using the traditional adjoint network method. Compared to the previous localized power grid fixing work with GridNet, GridNetOpt leads to smaller area overhead for all the benchmarks we tested. It can also reduce IR drops for power grid circuits with immortal wires, which is not possible with the localized GridNet method.

Experimental Validation of a Novel Methodology for Electromigration Assessment in On-Chip Power Grids

A recently proposed theoretical methodology for the assessment of the electromigration (EM) induced IR-drop degradation in on-chip power/ground grids has been validated by means of measurements performed on real silicon. A voltage tapping technique was employed for the direct measurement of voltage variations at 162 nodes of the power net, stressed with 10 mA constant source current at an elevated temperature of 350 °C. A voltage drop between cathode and anode pads exceeding a specified threshold was considered as a failure. Times-to-failure (TTF) was measured on 19 packaged test grids and used for computing the mean TTF (MTTF). The EM-induced voltage degradation in this grid was also analyzed with an assessment methodology based on a simulation of stress evolution everywhere in the grid, resulting in a voiding in some of grid branches and corresponding resistance increase. A set of voiding compact models for different grid segments was developed and used in the simulations. The stochastic nature of the EM phenomenon was captured by introducing random distributions of atomic diffusivities and critical stresses across the grid and iterating them with Monte Carlo loops. A good fit between the measured voltage evolution kinetics at different grid nodes and that predicted by simulation, and the good agreement between measured and simulated failure distributions can be considered as the ever first experimental validation of this EM assessment methodology for on-chip power/ground (p/g) grids.

Reduced Order Method for Solving Large-Scale Quadratic Eigenvalue Problems

Quadratic eigenvalue problems are frequently encountered in electromagnetic analysis of lossy dielectrics and conductors. We present a fast method for solving large-scale quadratic eigenvalue problems. The method reduces the order of the original quadratic eigenvalue problem to a small one to solve. The computational cost of the reduction is simply a small number of solutions of an underlying deterministic problem, which are obtained in linear complexity. Applications to electromagnetics-based analysis of large-scale on-chip power grids demonstrate the accuracy and efficiency of the method.

PGOpt: Multi-objective design space exploration framework for large-Scale on-chip power grid design in VLSI SoC using evolutionary computing technique

Design of the power grid network (PGN) of a VLSI chip is a challenging task because of the increase in network complexity. Due to the presence of resistances of the metal lines of the PGN, voltage drops occur in the form of IR drop, which can change the voltage level of underlying logic circuits, resulting in malfunction of the System-on-Chip (SoC). The IR drop also depends upon different reliability constraints, and violation of those constraints can deteriorate the IR drop much more. Subsequently, a significant objective while designing a PGN is to reduce the IR drop without violating the reliability constraints. IR drop also affects the timing of the critical path of the circuits. Over the past two decades, several works have been proposed to optimize the PGN by minimizing metal area considering the IR drop as a design constraint. One of the widely accepted IR drop minimization practices is by increasing the metal widths, which in turn increases the metal area. As a result, the area of the chip increases, which manifests that the primary design objectives, i.e., IR drop and metal routing area, are conflicting in nature. Therefore, these two conflicting design objectives need to be accommodated while designing the PGN in order to optimize the reliability and the yield of the chip. In this work, for the first time, we propose a multiobjective design space exploration framework for the power grid design, which deals with reliability and yield. We have studied various design aspects to determine a trade-off between these two critical conflicting design objectives by developing an optimization framework using the evolutionary algorithmic technique. Results on the standard power grid benchmarks demonstrate that our proposed framework helps in a reliable PGN design with high yield.

Robust power grid network design considering EM aging effects for multi-segment wires

This paper presents a number of power grid network design and optimization techniques that consider the electromigration (EM) effects for multi-segment interconnect wires. First, we consider a new EM immortality constraint due to EM void saturation volume for multi-segment interconnects. It helps reduce conservativeness in the EM-aware on-chip power grid design. Along with the EM nucleation phase immortality constraint, we show that both EM immortality constraints can be naturally integrated into the existing programming based power grid optimization framework. Second, to mitigate the overly conservativeness of the immortality constrained optimization methods, we further explore three strategies: we first size up failed wires to meet one of the immortality conditions subject to the design rules; second, we consider the EM-induced aging effects on power supply networks for a target lifetime, which allows some short-lived wires to fail and optimizes the remaining wires; third, we propose a large change sensitivity-based optimization scheme to perform localized fixing based on recently proposed coupled EM-IR drop analysis method. Numerical results on a number of IBM-format power grid networks demonstrate that the new method can reduce more power grid area compared to the existing EM immortality constrained optimizations. Moreover, the new method is able to optimize power grids with nucleated wires, which would not be possible with the existing methods. Results also show the sensitivity-based localized power girds fixing can fix EM-induced IR drop violations in a few minutes for synthesized power grid networks from ARM core designs.

Machine Learning Approach for Fast Electromigration Aware Aging Prediction in Incremental Design of Large Scale On-chip Power Grid Network

With the advancement of technology nodes, Electromigration (EM) signoff has become increasingly difficult, which requires a considerable amount of time for an incremental change in the power grid (PG) network design in a chip. The traditional Black’s empirical equation and Blech’s criterion are still used for EM assessment, which is a time-consuming process. In this article, for the first time, we propose a machine learning (ML) approach to obtain the EM-aware aging prediction of the PG network. We use neural network--based regression as our core ML technique to instantly predict the lifetime of a perturbed PG network. The performance and accuracy of the proposed model using neural network are compared with the well-known standard regression models. We also propose a new failure criterion based on which the EM-aging prediction is done. Potential EM-affected metal segments of the PG network is detected by using a logistic-regression--based classification ML technique. Experiments on different standard PG benchmarks show a significant speedup for our ML model compared to the state-of-the-art models. The predicted value of MTTF for different PG benchmarks using our approach is also better than some of the state-of-the-art MTTF prediction models and comparable to the other accurate models.

Fast Physics-Based Electromigration Analysis for Full-Chip Networks by Efficient Eigenfunction-Based Solution

Electromigration (EM) becomes one of the most challenging reliability issues for current and future ICs in 10-nm technology and below. In this article, a novel method is proposed for the EM hydrostatic stress analysis on 2-D multibranch interconnect trees, which is the foundation of the EM reliability assessment for large-scale on-chip interconnect networks, such as on-chip power grid networks. The proposed method, which is based on an eigenfunction technique, could efficiently calculate the hydrostatic stress evolution for multibranch interconnect trees stressed with different current densities and nonuniformly distributed thermal effects. The proposed method solves the partial differential equations of transient EM stress more efficiently since it does not require any discretization either spatially or temporally, which is in contrast to numerical methods, such as the finite difference method and finite element method. The accuracy of the proposed transient analysis approach is validated against the analytical solution and commercial tools. The convergence of the proposed method is demonstrated by numerical experiments on practical power/ground networks, showing that only a small number of eigenfunction terms are necessary for the accurate solution. Thanks to its analytical nature, the proposed method is also utilized in efficient EM analysis techniques, such as searching for the void nucleation time by a modified bisection algorithm. The numerical results show that the proposed method is 10X–100X faster than the finite difference method and scales better for larger interconnect trees.

Real-Time Detection of Power Analysis Attacks by Machine Learning of Power Supply Variations On-Chip

Reliably and power efficiently securing integrated systems against advanced power analysis attacks (PAAs) is a significant design challenge in modern integrated circuits. Power masking and hiding are typical countermeasures for increasing system resilience for power attacks at the expense of the overall system performance and power efficiency. These method are, however, not able to alert the user or trigger additional protective actions in case of the attack. In this paper, a method for detecting power attacks in real-time is proposed. The proposed approach exploits statistical methods to analyze the on-chip voltage variations across an on-chip power grid and detect the attacker probe connected to the system. The problem of the full security coverage of the power grid is formulated and solved in this paper. Adjusting the density of the on-chip sensors and exploiting sparse analysis techniques is considered to simultaneously enhance the accuracy and power efficiency of the proposed solution. The proposed attack detection system is designed, simulated, and evaluated in Simulink based on IBM microprocessor benchmark data. Machine learning (ML) models are trained in Python and with scikit-learn ML library. The proposed system has been demonstrated to efficiently detect PAA within a period of time that is orders of magnitude shorter than a typical attack duration length. The system is expected to exhibit high detection accuracy and power efficiency across a wide spectrum of integrated systems.

Optimal Allocation of LDOs and Decoupling Capacitors within a Distributed On-Chip Power Grid

Parallel on-chip voltage regulation, where multiple regulators are connected to the same power grid, has recently attracted significant attention with the proliferation of small on-chip voltage regulators. In this article, the number, size, and location of parallel low-dropout (LDO) regulators and intentional decoupling capacitors are optimized using mixed integer non-linear programming formulation. The proposed optimization function concurrently considers multiple objectives such as area, power noise, and overall power consumption. Certain objectives are optimized by putting constraints on the other objectives with the proposed technique. Additional constraints have been added to avoid the overlap of LDOs and decoupling capacitors in the optimization process. The results of an optimized LDO allocation in the POWER8 chip is compared with the recent LDO allocation in the same IBM chip in a case study where a 20% reduction in the noise is achieved. The results of the proposed multi-criteria objective function under a different area, power, and noise constraints are also evaluated with a sample ISPD’11 benchmark circuits in another case study.

Probabilistic Wire Resistance Degradation Due to Electromigration in Power Grids

Electromigration (EM) is a growing concern in on-chip interconnects, particularly in the computing and automotive domains. EM can cause wire resistances in a circuit to increase, which may result in circuit performance failure within the lifetime of a product. Classical circuit-level EM models have two drawbacks: first, they do not accurately capture the physics of degradation in modern copper dual-damascene (Cu DD) metallization and second, they fail to model the inherent resilience in a circuit that may allow it to continue to function even after some wires fail. This paper overcomes both limitations, and develops a method to analyze the effect of EM on the resistance of wires in a circuit. For a single wire, our probabilistic analysis encapsulates known realities about Cu DD wires, e.g., that some regions of these wires are more susceptible to EM than others, and that void evolution shows statistical behavior. We develop a new criterion for identifying mortal wires based on this analysis. One part of the criterion incorporates the achievement of steady state and provides a result that is slightly tighter than the traditional Blech criterion, while another part is tied to the lifetime of the system. We apply these ideas to the analysis of on-chip power grids and demonstrate the inherent robustness of these grids that maintains supply integrity under some EM failures.

A Multiphase Switched-Capacitor DC–DC Converter Ring With Fast Transient Response and Small Ripple

A fully integrated step-down switched-capacitor dc–dc converter ring with 123 phases has been designed that could achieve fast dynamic voltage scaling for the microprocessor of wearable devices. The symmetrical multiphase converter ring surrounds its load in the square and supplies power to the on-chip power grid that is easily accessible at any point of the chip edges. The frequency of the $V_{\mathrm {DD}}$ -controlled oscillator is adjusted through its supply voltage $V_{\mathrm {DD}}$ , which allows the unity-gain frequency to be designed higher than the switching frequency. The converter ring has been fabricated in a low-leakage 65-nm CMOS process. This converter achieves a response time of 3 ns, a reference tracking speed of 2.5 V/ $\mu \text{s}$ , and a minimum output ripple of 2.2 mV. The peak efficiency is 80% at the power density of 66.6 mW/mm2, and the maximum power density is 180 mW/mm2.

Power integrity modeling and measurement of TSV-based 3D IC system with application to the analysis of seven-chip stack

This paper presents power integrity modeling and measurement of through-silicon via (TSV)-based 3D IC system. To leverage the accuracy of a full-wave approach and shorter computational time of a circuit approach, a hybrid full-wave and circuit approach is proposed to model each individual chip consisting of TSVs, on-chip power grids and decoupling capacitors. A cascaded scattering matrix approach is used to model the 3D IC system by combining the results for individual chips, packages and boards. The hybrid modeling approach is demonstrated on a 7-chip stack consisting of 6 via-last and 1 via-middle chips. Modeling results show good correlation with measurement from 0.1 GHz to 20.1 GHz. Power integrity analysis is performed to show the effects of TSVs and vertical natural capacitors (VNCAPs) on the power distribution network in individual chips and the 7-chip stack. The passive VNCAPs in the 7-chip stack are also compared with active capacitors based on measurement. Finally, both modeling and measurement results for a prototype consisting of the 7 stacked chips mounted on a BGA substrate and a PCB are presented. This is probably the first comprehensive power integrity modeling, measurement and analysis of such a complete TSV-based 3D IC system at both chip and board levels.

Transient Electrical-Thermal Analysis of 3-D Power Distribution Network With FETI-Enabled Parallel Computing

In this paper, the transient electrical-thermal co-simulation is implemented with the finite-element method. The capability of the co-simulation is extended to solve large-scale problems by incorporating a domain decomposition scheme called the finite element tearing and interconnecting (FETI). With the high parallel efficiency of FETI for computing with multiple processors, a significant reduction in computation time is achieved. The transient electrical-thermal behaviors of largescale power distribution networks (PDNs), including on-chip power grids, solder bump arrays, and TSV-based PDN are simulated and analyzed with the proposed method. The impacts on the design of the PDNs from different types of input pulses, power maps, and via pitches are also investigated.

Worst Case Noise Prediction With Nonzero Current Transition Times for Power Grid Planning

In this paper, we propose a novel method for power distribution network verification at early design stages. This approach predicts the worst case noise of on-chip power grids with multiple current sources subjected to a set of hierarchical constraints. The current constraints not only define bounds for current magnitudes, but also consider nonzero current transition times that makes the prediction of worst case noise more realistic. Under the novel current constraints, a dynamic programming algorithm is introduced to generate the worst case current sources based on the impulse responses of the power grid. The algorithm is accelerated by a modified Knuth-Yao quadrangle inequality speedup method, which reduces the time complexity from O(s2m) to O(smlogs), where s is the number of discretized current values and m is the total number of zero-crossing points of the current sources. Experimental results show that our approach not only efficiently predicts realistic worst case noise of on-chip power grids, but also correlates the frequency-domain resonance effects with the time-domain noise behavior.

Electromagnetic-Simulation Program With Integrated Circuit Emphasis Modeling, Analysis, and Design of 3-D Power Delivery

Accurate modeling and estimation of 3-D power network electrical performance are vitally important to aid 3-D integration and packaging design. This paper, for the first time, combines the electromagnetic (EM) simulation program with integrated circuit emphasis simulations to evaluate the electrical performance of a 3-D power network, which consists of Cu through-silicon-vias (TSVs), solders, micro-solders, and on-chip power grids. We intentionally partition a real stack-up structure of 3-D power network into separated components, electromagnetically extract all the passive elements resistance, inductance, conductance, and capacitance (RLGC) for each component at certain frequency points of interest. We then assemble all the components again into a corresponding equivalent circuit model and import EM-extracted RLGC values to analyze the overall 3-D system power performance. The number of stacked integrated circuits, floorplanning of TSVs/micro-solders, operating frequency of 3-D system, characteristics of decoupling capacitance, size of on-chip power grids, parasitics of power wires/vias/solders/TSVs/micro-solders, voltage supply, and waveform parameters of current loads are examined, unveiling several 3-D power delivery design implications.

IC power delivery

Modern IC power delivery systems encompass large on-chip passive power grids and active on-chip or off-chip voltage converters and regulators. While there exists little work targeting on holistic design of such complex IC subsystems, the optimal system-level design of power delivery is critical for achieving power integrity and power efficiency. In this article, we conduct a systematic design analysis on power delivery networks that incorporate Buck Converters (BCs) and on-chip Low-Dropout voltage regulators (LDOs) for the entire chip power supply. The electrical interactions between active voltage converters, regulators as well as passive power grids and their influence on key system design specifications are analyzed comprehensively. With the derived design insights, the system-level codesign of a complete power delivery network is facilitated by a proposed automatic optimization flow in which key design parameters of buck converters and on-chip LDOs as well as on-chip decoupling capacitance are jointly optimized. The experimental results demonstrate significant performance improvements resulted from the proposed system cooptimization in terms of achievable area overhead, supply noise and power efficiency. Impacts of different decoupling capacitance technologies are also investigated.

레이아웃 기반 온-칩 전력 분배 격자 구조의 인덕턴스 모델 개발 및 적용

With the lower supply voltage and the higher operating frequency in integrated circuits, the analysis of the power distribution network (PDN) including on-chip inductances becomes more important. In this paper, an effective inductance extraction method for a regular on-chip power grid structure is proposed. The loop inductance model applicable to chip layout is proposed and the inductance extraction tool using the proposed inductance model based on post layout RC circuits is developed. The accuracy of the proposed loop model and the developed tool is verified by comparing the test circuit simulation results with those from the partial element equivalent circuit (PEEC) model. The voltage fluctuation from the RLC circuits extracted by the developed tool was examined for the analysis of on-chip inductance effects. The significance of on-chip power grid inductance was investigated by the co-simulation of chip-package-PCB.

Decentralized and Passive Model Order Reduction of Linear Networks With Massive Ports

It is well known that model order reduction for circuits with many terminals remains a challenging problem. One reason is that existing approaches are based on a centralized framework, in which each input-output pair is implicitly assumed to be equally interacted and the matrix-valued transfer function is assumed to be fully populated. In this paper, we attempt to address this long-standing problem using a decentralized model order reduction scheme, in which a multi-input multi-output system is decoupled into a number of subsystems and each subsystem corresponds to one output and several dominant inputs. The decoupling process is based on the relative gain array, which measures the degree of interaction of each input-output pair. For each decoupled subsystem, passive reduction can be easily achieved using existing reduction techniques. The proposed method is suitable for resistance-dominant interconnects such as on-chip power grids, substrate planes where extremely compact models can be obtained. Simulation results demonstrate the advantage of the proposed method compared to the existing approaches.

Novel closed-form resistance formulae for rectangular interconnects

Two closed-form formulae for the frequency-dependent resistance of rectangular cross-sectional interconnects are presented. The frequency-dependent resistance R(f) of a rectangular interconnect line or a interconnect line with a ground plane structure is first obtained by a numerical method. Based on the strict numerical results, a novel closed-form formula R (f) for a rectangular interconnect alone is fitted out using the Levenberg—Marquardt method. This R(f) can be widely used for analyzing on-chip power grid IR-drop when the frequency is changing. Compared to the previously published R(f) formula for an interconnect, the formula provided here is more accurate during the frequency transition range. Also for a bigger width to thickness ratio, this formula shows greater accuracy and robustness. In addition, this paper fits out the closed-form R(f) formula for a micro-strip-like interconnect (an interconnect with a ground plane), which is a typical structure in the on-chip or package power delivery system.

Stochastic Non-homogeneous Arnoldi Method for Analysis of On-Chip Power Grid Networks under Process Variations

In this paper, a Stochastic Non-Homogeneous ARnoldi (SNHAR) method is proposed for the analysis of the on-chip power grid networks in the presence of process variations. In SNHAR method, the polynomial chaos based stochastic method is employed to handle the variations of power grids. Different from the existing StoEKS method which uses extended Krylov Subspace (EKS) method to compute the coefficients of the polynomial chaos, a computation-efficient and numerically stable Non-Homogeneous ARnoldi (NHAR) method is employed in SNHAR method to compute the coefficients of the polynomial chaos. Compared with EKS method, NHAR method has superior numerical stability and can achieve remarkably higher accuracy with even lower computational cost. As a result, SNHAR can capture the stochastic characteristics of the on-chip power grid networks with higher accuracy, but even lower computational cost than StoEKS.