PGOpt: Multi-objective design space exploration framework for large-Scale on-chip power grid design in VLSI SoC using evolutionary computing technique

Abstract

Design of the power grid network (PGN) of a VLSI chip is a challenging task because of the increase in network complexity. Due to the presence of resistances of the metal lines of the PGN, voltage drops occur in the form of IR drop, which can change the voltage level of underlying logic circuits, resulting in malfunction of the System-on-Chip (SoC). The IR drop also depends upon different reliability constraints, and violation of those constraints can deteriorate the IR drop much more. Subsequently, a significant objective while designing a PGN is to reduce the IR drop without violating the reliability constraints. IR drop also affects the timing of the critical path of the circuits. Over the past two decades, several works have been proposed to optimize the PGN by minimizing metal area considering the IR drop as a design constraint. One of the widely accepted IR drop minimization practices is by increasing the metal widths, which in turn increases the metal area. As a result, the area of the chip increases, which manifests that the primary design objectives, i.e., IR drop and metal routing area, are conflicting in nature. Therefore, these two conflicting design objectives need to be accommodated while designing the PGN in order to optimize the reliability and the yield of the chip. In this work, for the first time, we propose a multiobjective design space exploration framework for the power grid design, which deals with reliability and yield. We have studied various design aspects to determine a trade-off between these two critical conflicting design objectives by developing an optimization framework using the evolutionary algorithmic technique. Results on the standard power grid benchmarks demonstrate that our proposed framework helps in a reliable PGN design with high yield.