PGRDP: Reliability, Delay, and Power-Aware Area Minimization of Large-Scale VLSI Power Grid Network Using Cooperative Coevolution

Abstract

Power grid network (PGN) of a VLSI system-on-chip (SoC) occupies a significant amount of routing area in a chip. As the number of functional blocks is increasing in an SoC chronologically, the need of the hour is to have more power lines in order to provide adequate power connections to the extra-added functional blocks. Therefore, to accommodate more functional blocks in the minimum area possible, the PGN should also have minimum area. Minimization of the area can be achieved by relaxing few power grid constraints. In view of this, due to the resistance of the PGN, it suffers from considerable reliability issues such as voltage drop noise and electromigration. Further, it also suffers from the interconnect delay and power dissipation due to its parasitic resistances and capacitances. These PGN constraints should be relaxed up to a certain limit, and the area minimization should be done accordingly. Therefore, in this paper, we have considered an RC model of the PGN and formulated the area minimization for PGN as a large-scale minimization problem considering different reliability, delay, and power-aware constraints. Evolutionary computation-based cooperative coevolution technique has been used to solve this large-scale minimization problem. The proposed method is tested on industry-based power grid benchmarks. It is observed that significant metal routing area of the PGN has been reduced using the proposed method.