Probabilistic Wire Resistance Degradation Due to Electromigration in Power Grids

Abstract

Electromigration (EM) is a growing concern in on-chip interconnects, particularly in the computing and automotive domains. EM can cause wire resistances in a circuit to increase, which may result in circuit performance failure within the lifetime of a product. Classical circuit-level EM models have two drawbacks: first, they do not accurately capture the physics of degradation in modern copper dual-damascene (Cu DD) metallization and second, they fail to model the inherent resilience in a circuit that may allow it to continue to function even after some wires fail. This paper overcomes both limitations, and develops a method to analyze the effect of EM on the resistance of wires in a circuit. For a single wire, our probabilistic analysis encapsulates known realities about Cu DD wires, e.g., that some regions of these wires are more susceptible to EM than others, and that void evolution shows statistical behavior. We develop a new criterion for identifying mortal wires based on this analysis. One part of the criterion incorporates the achievement of steady state and provides a result that is slightly tighter than the traditional Blech criterion, while another part is tied to the lifetime of the system. We apply these ideas to the analysis of on-chip power grids and demonstrate the inherent robustness of these grids that maintains supply integrity under some EM failures.